Final Thoughts

ARM has certainly been busy, refreshing several key technologies for the next generation of SoCs. DynamIQ might not be as flashy as a new CPU, but as a replacement for big.LITTLE it’s every bit as important. It will be interesting to see how ARM’s partners utilize its flexibility. Will we continue to see the same 4+4 combination of big and little cores at the high end and 8 little cores in the low end to midrange? Or will we see new 7+1 or 3+1 combinations with a single A75 surrounded by A55s? Currently only the A75/A55 are compatible with DynamIQ, and the new CPUs cannot be mixed with older cores using big.LITTLE. This means we will not see the A35 used in mobile outside of MediaTek’s Helio X30.

DynamIQ is an upgrade to bL in other ways too. Placing both the big and little cores inside the same cluster brings several benefits: making the L2 caches local to each CPU and adding an optional L3 cache improves overall memory performance, thread migration latency is reduced, and CPUs can be powered up/down more quickly, which could lead to better battery life.

The A55’s extra performance is a welcome change. This should yield tangible improvements to the user experience in mobile applications, certainly for devices that use A55 cores exclusively. Even devices with A75 cores should still see some benefit considering how threads spend most of their time running on the little cores.

ARM already pushed throughput through the A53’s 2-wide in-order core about as far as it could. Given the power and area targets for A53/A55, going wider or out of order are not possible at this stage. Instead, ARM focused on improving the memory system, reducing latency and improving utilization of the in-order core by keeping it fed with data. The increased performance comes with a small bump in power, but overall efficiency is better.

For the A75, the move to 3-wide decode, improvements throughout the cache hierarchy, and tweaks to improve its out-of-order capability should yield clear performance gains over the A73 in both integer and floating-point workloads. At the same frequency, the A72 actually performs better than A73 in some situations. I expect this will not be the case with A75.

According to ARM’s numbers, the A75’s performance gains help it maintain the same efficiency as the A73, but power consumption is higher, which concerns me a little. ARM has an implementation team optimizing its reference design, so its power numbers are sort of a target for SoC vendors. Because of pressure to reduce time to market, vendors do not always have the same amount of time to optimize their designs, resulting in higher power consumption and lower efficiency. Hopefully, vendors put in the effort to match or get close to ARM’s numbers.

ARM’s primary goal for A72 was reducing power, for A73 it was improving power efficiency, and for A75 it's improving performance. What will be the goal for the next core, which will be coming from ARM’s Austin team that produced the A72? Will it look similar to A75, or will there be a significant shift in philosophy like we saw with A72 to A73? There is communication and cross pollination of ideas between teams so there's sure to be some similarities, especially with the execution pipes. The biggest changes should be in the front end, and I would not be surprised to see an extra ALU pipe with the move to 7nm.

If all goes according to plan, we should see the first SoCs using DynamIQ and the A75/A55 in Q1 2018 (maybe Q4 2017) on 10nm.

Cortex-A55 Microarchitecture
POST A COMMENT

104 Comments

View All Comments

  • colinw - Monday, May 29, 2017 - link

    Motion to call "cache stashing" just "staching". All in favour say aye. Reply
  • R0H1T - Monday, May 29, 2017 - link

    Nay, motion denied due to lack of quorum. Reply
  • 0ldman79 - Monday, May 29, 2017 - link

    Motion is seconded. Reply
  • boeush - Tuesday, May 30, 2017 - link

    I vote for "cashing" as a write-in Reply
  • Alexvrb - Tuesday, May 30, 2017 - link

    I vote for 'staching as a write-in. Reply
  • nonz - Wednesday, May 31, 2017 - link

    Sheesh, it should obviously be called 'cache me outside' Reply
  • Eden-K121D - Monday, May 29, 2017 - link

    They could've​ improved the A55 quite a bit more Reply
  • lilmoe - Monday, May 29, 2017 - link

    It's a start. There's only so much you can do and stay in-order. Reply
  • Samus - Monday, May 29, 2017 - link

    It isn't that bad for a YoY gap, but you are right, it's been two years...and let's face it, the little core is actually more important because that's where battery life improvements are made. Reply
  • aryonoco - Monday, May 29, 2017 - link

    A53 was announced in 2013. First SoCs implementing it came out in 2014.

    A55 is being announced in 2017, SoCs implementing it will probably come out in 2018.

    So it's a 4 year gap, not two.

    Fact is, there is only so much you can do with an in-order die-constrained design.
    Reply

Log in

Don't have an account? Sign up now