PCI Express: Interconnect of the future

Intel proposed the original PCI 1.0 specification back in 1991. The PCI Special Interest Group (which took over development of PCI), produced revision 2.0 in May 1993.

Its rival at the time was the VESA Local Bus (VL-bus or VLB). Introduced by the Video Electronics Standards Association, VL-bus was a 32-bit bus that involved a third and forth connector appended to the end of a regular ISA slot. It ran at a nominal speed of 33MHz and offered significant performance over ISA.

One of the main features that provided such great performance was, ironically, one of the main factors in VLB's downfall. It was essentially a direct extension of the 486 processor/memory bus, running at the same speed as the processor, hence the name "local bus". This direct extension meant that connecting too many devices risked interfering with the processor itself, particularly if the signals went through a slot. VESA recommended that only two slots be used at clock frequencies up to 33MHz, or three if they were electrically buffered from the bus. At higher frequencies no more than two devices should be connected, and at 50MHz or above they should both be built into the motherboard.

Because the VL-bus ran synchronously with the processor, increasing processor frequencies caused real problems for VL-bus peripherals. The faster the peripherals are required to run, the more expensive they are, due to the difficulties associated with manufacturing high-speed components. Very few VL-bus components were built to handle speeds in excess of 40MHz.

PCI had some compelling advantages over VL-bus. It was designed as a mezzanine bus: PCI was a separate bus isolated from CPU, but still had access to main memory.

It had the ability to run asynchronously from the processor, with the nominal speeds of 25MHz, 30MHz and 33MHz. As processor speeds increased, the PCI bus speed could remain constant, as it ran at an adjustable fraction of the front side bus. The maximum number of slots and/or peripherals allowed by PCI, 5 or more, doubled what the VL-bus could handle, without any restrictions set by bus speed, buffering or other electrical considerations.

Other "smart" features promoted ease of use. Plug and Play allowed automatic configuration of peripherals without the need to set IRQ jumpers, DMA and IO addresses. It allowed IRQs to be shared, as well as having its own interrupt system (hidden away as #A, #B, #C and #D).

Finally, PCI bus mastering allows devices on the PCI bus to take control of the bus and perform transfers directly without CPU arbitration. This lowers latency and processor usage.

Its introduction alongside the Pentium processor, along with its clear benefits over rival buses at the time, helped PCI emerge from the bus wars as the dominant standard in 1994. Since then, just about all peripheral devices, from hard disk controllers, sound cards, to NICs and video cards, have been PCI based.