PCI Express: Interconnect of the future

With the advent of RAID arrays, Gigabit Ethernet and other high bandwidth devices on consumer class systems, PCI's 133MB/s available bandwidth is clearly insufficient to handle these demands.

Chipset makers have foreseen this limitation and have made various changes to motherboard chipsets in order to alleviate some of the load from the PCI bus.

Up until 1997, graphics data was probably the single largest cause of traffic on the PCI bus. The Accelerated Graphics Port (AGP), introduced by Intel's 440LX chipset, had two main purposes: to increase graphics performance and to pull the graphics data off the PCI bus. With graphics data transfers taking place on another "bus" (technically, AGP is not a bus, since it only supports one device), the previously saturated PCI bus was freed up for use with other devices.

Yet AGP was just one step in reducing the load on the PCI bus. The next was to redesign the link between the North Bridge and South Bridge of motherboard chipsets. Older chipsets, such as the Intel 440 series used a single PCI bus to connect the North Bridge to the South Bridge. The PCI bus not only had to cope with inter-bridge traffic, but it also had to carry regular PCI traffic, IDE, Super I/O (Serial, Parallel, PS/2), and USB. To alleviate the situation Intel, VIA and SiS replaced the PCI bus between the North and South Bridges with a High Speed interconnect, and then shifted IDE, Super I/O and USB to their own dedicated links to the South Bridge.

Now with Intel's Communications Streaming Architecture bus built into the Memory Controller Hub of the i875/i865 chipsets, even Gigabit Ethernet is off the PCI bus.

Numerous dedicated interconnects for various devices in the i875 chipset: not really a cost effective solution