ARM Challenging Intel in the Server Market: An Overview
by Johan De Gelas on December 16, 2014 10:00 AM ESTOverview of the Competitors
Let's sum everything up in one big table.
| ARM/Intel SoC 2015 Comparison | ||||||||
| SoC | Intel Xeon-D | Intel Atom C2000 | AppliedMicro X-Gene 1 (X-Gene 2) |
AMD A1100 | Cavium Thunder-X | Broadcom Vulcan | ||
| Architecture | Broadwell | Silvermont | Storm (ShadowCat) | A57 | Thunder-X | Vulcan | ||
| Cores Socket |
8 single |
8 single |
8 (16) sngle |
4-8 single |
16-48 dual |
20? | ||
| Max. CPU Clockspeed | GHz | 2.4GHz | 2.4GHz (2.8GHz) |
2GHz | 2.5 Ghz | 3GHz | ||
| Process technology | Intel 14nm | Intel 22nm | TSMC 40nm (TSMC 28nm) |
GF 28nm | GF 28nm | TSMC 16nm | ||
| L1 Cache | 32KB I 32KB D |
32KB I 24KB D |
32KB I (*) 32KB D (*) |
48KB I 32KB D |
78KB I 32KB D |
32KB I 32KB D |
||
| Decode | 4 | 2 | 4 | 3 | 2 | 4 | ||
| Max. IPC (int) | 5 | 2 | 4 | 3 | 2 | 4 | ||
| Exe Ports | 8 | 4 | 8 | 8 | 4? | 6 | ||
| Max. FP Performance | 2x 256 bit | 1x 128 bit | 2x 128 bit | 2x 128 bit | 2x 128 bit | 2x 128 bit | ||
| OoO buffer | 192 | 32 | >100 | 128 | 40 | 180 | ||
| L2 Cache | 8x 256KB | 4x 1MB | 4x 256KB? (*) | 4x 1MB | 16MB | 20x 256KB | ||
| L3 Cache | 8MB? | - | 8MB | 8MB | - | ? | ||
| Max. RAM | 128GB | 64GB | 128GB | 128GB | 1TB | ? | ||
| Memory Bus Width | 2x 64-bit | 2 x 64-bit | 4x 64-bit | 2x 64-bit | 4x 64-bit | 4x 64-bit | ||
| DRAM (best) | DDR4- 2133 |
DDR3- 1600 |
DDR3- 1866 |
DDR3- 1866 |
DDR4- 2133 |
DDR4- 2133 |
||
| TDP (top SKU) | 45W | 20W | 40W (25 W?) |
25W | +/- 95 W | ? | ||
| Available | Q2-Q3 2015 |
Early 2014 |
Now (Q2 2015?) |
Q1-Q2 2015 |
Q1 2015 |
Q3 2015 |
||
(*) Deduced from Ganesh's article about the Helix SoCs
These are paper specifications of course, so they should be interpreted with a grain of salt. It looks like the AMD A1100 should top the Atom C2000 and go after the low end of the Xeon E3. AMD's Opteron A1100 is already available, but the current development kits do not hit the clock speed and performance targets.
The Thunder-X single-threaded performance in "traditional workloads" might only be at the level of the Atom C2000, but scale-out and network/crypto acceleration could give some remarkable results in certain workloads. The Cavium SoC is the hardest to predict and will show a very variable performance profile as it also incorporates many very specialized hardware accelerators. The Thunder-X reference servers are announced and should be available in the coming weeks.
The X-Gene is currently the widest ARM architecture with extra hardware acceleration mostly focused on networking. The X-Gene TDP was great on paper (25W when announced) but there are many indications (40W TDP) that AppliedMicro really needs the 28nm X-Gene 2 to be truly competitive in the performance/watt battle arena. The X-Gene 2 should be available around Q2 2015.
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patrickjchase - Thursday, December 18, 2014 - link
It's been a while since I worked on this stuff, but I don't think that the statement that "CCN is very comparable to the ring bus found inside all Xeon processors beginning with Sandy Bridge" is quite right.CCN
patrickjchase - Thursday, December 18, 2014 - link
Finishing my comment:CCN
stefstef - Wednesday, December 17, 2014 - link
the idea of having an energy efficient design certainly will pay off. nvidia and samsung showed that having i.e. 4 cores and a fifth core dedicated to the energy management can be a good low cost solution. i dont often read the articles at anandtech because they are usually boring. although i am happy to place a coment here. arm rules in certain fields but in a couple of years only because intel will allow them to do so. every company needs a room to live in. another american breakfast for the chinese who will get their share in the processor market as well.milli - Thursday, December 18, 2014 - link
I don't understand how ARM is suddenly going to succeed while MIPS and PowerPC have already tried and failed. I feel that ARM is more of a market trend than anything else (in the server market).Even the current ARM server SOC manufacturers have already tried to penetrate the server market. Cavium and Broadcom already had custom designed low-power MIPS SOCs. IBM, Applied Micro and Freescale have had a bunch of low-power PowerPC options.
By the time any of these products is released, Intel is going to have a better alternative thanks to their process advantage. No IT manager is going to manage to convince any of the corporate fat-cats that a huge overhaul is needed. Same story over again.
yuhong - Friday, December 19, 2014 - link
"Unfortunately their 16GB DIMMs will only work with the Atom C2000, leading to the weird situation that the Atom C2000 supports more memory than the more powerful Xeon E3."I think the reason is software related. More precisely, the Memory Reference Code (MRC).
intiims - Tuesday, December 30, 2014 - link
If You want to know something about External Hard Drives visit http://www.hddmag.com/adrian1987 - Monday, January 5, 2015 - link
Hi. The Haswell core can actually have a max IPC of 6 instructions per cycle using macro-fusion not 5 as listed here (assuming the code is ideal). It has 2 execution units that can handle fused ALU and branch instructions. Source: http://www.anandtech.com/show/6355/intels-haswell-...aaronjoue - Tuesday, April 7, 2015 - link
Here is the real micro server. http://www.ambedded.com.tw/pt_list.php?CM_ID=20140...http://wiki.ambedded.com.tw/index.php?title=MicroS...
7 & 21 nodes in a chassis
It support Ubuntu and open source Ceph.