The Evolving Server Market

The previous page might give you the impression that we do not give the ARM players a chance against mighty Intel. That is not the case, but we believe that the wrong arguments are often used. Intel's success was also a result of the huge amount of Windows desktop users that were enthusiastic about using their Windows knowledge in a professional environment. The combination of Windows NT and the success of the Pentium Pro was very powerful.

ARM also has such a "Trojan software horse" and it is called the Linux based cloud. We're not saying anything new when we say that cloud services have really taken off and that the Internet of Things will make cloud services even more important. Those cloud services have been creating a tsunami of innovation and are based on open source projects such as Hadoop, Spark, Openstack, MongoDB, Cassandra, good old Apache, and hundreds of others. That software stack is ported or being ported to the ARM software ecosystem.

But you probably knew that. Let's make it more concrete. Just a while ago we visited the Facebook hardware lab. Being a server hardware enthusiast, we felt like a child in a large toy store. Let me introduce you to Facebook's Open Vault, part of the the Open Compute Project:

... is a simple and cost-effective storage solution with a modular I/O topology that’s built for the Open Rack. The Open Vault offers high disk densities, holding 30 drives in a 2U chassis, and can operate with almost any host server.

Mat Corddry, director of hardware of engineering showed us the hardware:

The first incarnation of the "honey badger" micro server is based on Avoton. But nothing is stopping Facebook from using an ARM micro server in their Open Vault machines if it offers the same capabilities and is cheaper and/or lower power. As cheap storage is extremely important in the "Big Data" age, this is just one of the opportunities that the "smaller" ARM server SoCs have. But it also makes another point: they have to beat the Intel SoCs that are already known and used.

Are Economies of Scale and Volume Enough? The RISC Advantage
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  • patrickjchase - Thursday, December 18, 2014 - link

    It's been a while since I worked on this stuff, but I don't think that the statement that "CCN is very comparable to the ring bus found inside all Xeon processors beginning with Sandy Bridge" is quite right.

    CCN
  • patrickjchase - Thursday, December 18, 2014 - link

    Finishing my comment:

    CCN
  • stefstef - Wednesday, December 17, 2014 - link

    the idea of having an energy efficient design certainly will pay off. nvidia and samsung showed that having i.e. 4 cores and a fifth core dedicated to the energy management can be a good low cost solution. i dont often read the articles at anandtech because they are usually boring. although i am happy to place a coment here. arm rules in certain fields but in a couple of years only because intel will allow them to do so. every company needs a room to live in. another american breakfast for the chinese who will get their share in the processor market as well.
  • milli - Thursday, December 18, 2014 - link

    I don't understand how ARM is suddenly going to succeed while MIPS and PowerPC have already tried and failed. I feel that ARM is more of a market trend than anything else (in the server market).
    Even the current ARM server SOC manufacturers have already tried to penetrate the server market. Cavium and Broadcom already had custom designed low-power MIPS SOCs. IBM, Applied Micro and Freescale have had a bunch of low-power PowerPC options.
    By the time any of these products is released, Intel is going to have a better alternative thanks to their process advantage. No IT manager is going to manage to convince any of the corporate fat-cats that a huge overhaul is needed. Same story over again.
  • yuhong - Friday, December 19, 2014 - link

    "Unfortunately their 16GB DIMMs will only work with the Atom C2000, leading to the weird situation that the Atom C2000 supports more memory than the more powerful Xeon E3."
    I think the reason is software related. More precisely, the Memory Reference Code (MRC).
  • intiims - Tuesday, December 30, 2014 - link

    If You want to know something about External Hard Drives visit http://www.hddmag.com/
  • adrian1987 - Monday, January 5, 2015 - link

    Hi. The Haswell core can actually have a max IPC of 6 instructions per cycle using macro-fusion not 5 as listed here (assuming the code is ideal). It has 2 execution units that can handle fused ALU and branch instructions. Source: http://www.anandtech.com/show/6355/intels-haswell-...
  • aaronjoue - Tuesday, April 7, 2015 - link

    Here is the real micro server. http://www.ambedded.com.tw/pt_list.php?CM_ID=20140...
    http://wiki.ambedded.com.tw/index.php?title=MicroS...
    7 & 21 nodes in a chassis
    It support Ubuntu and open source Ceph.

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