MIPS Strikes Back: 64-bit Warrior I6400 Arrives
by Stephen Barrett on September 2, 2014 10:00 AM ESTFinal Words
When it comes to processors, enthusiasts and laymen alike can identify the three largest players: Intel, AMD and ARM. Those names are also not mutually exclusive: AMD utilizes ARM designs for consumer security coprocessors and in its Opteron A1100 server processor. There are other processors out there (e.g. IBM's POWER CPUs), but they're generally not as well known. That's also the case with MIPS.
Not everyone knows the name MIPS, but Imagination hopes to change that by offering a viable alternative to the embedded market dominated by ARM. MIPS already has a large presence in networking and embedded devices. Introducing the I6400 keeps MIPS relevant and places additional pressure on ARM. According to the provided numbers (admittedly from MIPS) and feature descriptions, the I6400 appears to compete with and even surpass the highly anticipated ARM Cortex-A53. Imagination projects general availability of the I6400 to SoC designers by December 2014. We can estimate end-user availability at least 6 to 9 months after that.
Consumers will most likely directly experience the MIPS I6400 CPU in low cost Android tablets and handsets. Due to Android's Java heritage, some applications will work out-of-the-box. Other applications using the Android Native Development Kit (NDK) targeting Intel or ARM ISAs will unfortunately be incompatible. Until MIPS achieves enough volume to convince application developers to code to the MIPS3264 ISA or stick with Java, MIPS Android devices will be second class citizens. This is something to keep in mind if you're purchasing a phone for yourself or a tech savvy friend. Of course, basic operating system features like email, phone, text, web browsing, and chatting should all work fine.
Intel has enjoyed dominance of its performance leading processors in non-handset settings for the better part of a decade. ARMs embedded low power heritage has emerged as Intel’s biggest threat as mobile devices have exploded and now dominate the computing landscape. As Intel and ARM continue to battle for the high end embedded market, Imagination and MIPS hope to erode away ARM’s mid-range and low-end core competency. As a consumer, we can lean back and enjoy the competition that will force each company to work harder each and every year.
The I6400’s revised MIPS3264 Release 6 ISA, instruction bonding, and SMT execution pipeline bring a refreshing set of new innovations to the small-core market. In our A53 coverage we noted ARM was pushing in-order CPU performance about as far as it could possibly go. I’m always happy to see we might have been wrong.
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flamethrower - Tuesday, September 2, 2014 - link
For me, I know MIPS because the Sony PSP (handheld game console) uses a MIPS, the MIPS R4000.alexvoica - Tuesday, September 2, 2014 - link
Nintendo 64 used MIPS too. On top of that, it was a 64-bit MIPS-based CPU!alexvoica - Tuesday, September 2, 2014 - link
Can't sleep so I'm doing a live MIPS AMA at http://redd.it/2f9c14 if anyone wants to join.name99 - Tuesday, September 2, 2014 - link
"If two load or store instructions arrive at the scheduler with adjacent addresses, the I6400 can "bond" them together into a single instruction executed by the load/store unit.
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Armv8 has essentially the same thing. Details differ, but there is an instruction that loads/stores two registers to adjacent memory locations as one operation --- same idea to utilize the full width of the 128bit bus to the cache.
Stephen Barrett - Tuesday, September 2, 2014 - link
Good to know. That is an ISA update though so it requires compiler support and a recompile. The MIPS feature is part of their hardware scheduler so they can do it on 32 bit programs and 64 bit programs simultaneously and without any updates to the programsWonderfulVoid - Tuesday, September 2, 2014 - link
Load/store dual (or double) is supported already on ARMv7A (infocenter.arm.com mentions support from ARMv5TE). These are 32-bit architectures but I am sure 64-bit ARMv8 can load/store 128 bits using equivalent instructions.Having the HW do it for you automatically is of course a nice feature. The end result might be the same.
Wilco1 - Tuesday, September 2, 2014 - link
Having separate instructions to do load/store double means smaller codesize - these instructions are commonly used during function prolog and epilog so they give significant gains.DMStern - Tuesday, September 2, 2014 - link
The MIPS r6 architecture is very interesting, because in order to clear opcode space, a number of rarely-used instructions have been deleted. Some architectural wart have also been removed, maybe most notably the branch delay slot instruction. This is the first time anything has been removed from the base ISA since its creation in 1985.WonderfulVoid - Tuesday, September 2, 2014 - link
Is MIPSr6 backwards compatible? Can you run earlier user and kernel space binaries on a MIPSr6 processor?Difficult to emulate the removed instructions if those opcodes are used for new instructions.
Maybe there is a need for a mode switch, r6 mode or pre-r6 mode?
DMStern - Tuesday, September 2, 2014 - link
It is not backwards compatible."In Release 6 implementations, object-code compatibility is not guaranteed when directly executing pre-Release 6 code, because certain pre-Release 6 instruction encodings are allocated to different instructions in Release 6."
Removing the delay slot of course also breaks binary compatibility in a major way. The documentation (which you can download from ImgTec's website) claims r6 has been designed to make translation of old binaries efficient.