3D NAND: Hitting The Reset Button on Scaling

Now that we understand how 3D NAND works, it is time to see what it is all about. As we now know, the problem with 2D NAND is the shrinking cell size and the proximity of the cells, which results in degraded reliability and endurance. Basically, 3D NAND must solve these two issues but it must also remain scalable to be economical. So how does it do that? This is where the third dimension comes into play.

The cost of a semiconductor is proportional to the die size. If you shrink the die, you effectively get more dies from a single wafer, resulting in a lower cost per die. Alternatively you can add more functionality (i.e. transistors) to each die. In the case of NAND, that means you can build a higher capacity die while keeping the die size the same, which gives more gigabits per wafer and thus reducing cost. If you cannot shrink the die, then you have just hit a dead-end because the cost will not scale. That is what has happened with 2D NAND because the shrinks on X and Y axes have run out of gas.

What 3D NAND does is add a Z-axis to the game. Because it stacks cells vertically, it is no longer as dependent on the X and Y axes since the die size can be reduced by adding more layers. As a result, Samsung's V-NAND takes a more relaxed position on the X and Y axes by going back to a 40nm process node, which increases the cell size and leaves more room between individual cells, eliminating the major issues 2D NAND has. The high amount of layers compensates for the much larger process node, resulting in a die that is the same size and capacity as the state of the art 2D NAND dies but without the caveats.

The above graph gives some guidance as to how big each cell in V-NAND really is. On the next page, I will go through the method of how cell size is really calculated and how V-NAND compares with Micron’s 16nm NAND but the above gives a good picture of the benefit that 3D NAND has. Obviously, when each cell is larger and the distance between individual cells is higher, there are more electrons to play with (i.e. more room for voltage state changes) and the cell to cell interference decreases substantially. Those two are the main reasons why V-NAND is capable of achieving up to ten times the endurance of 2D NAND.

Moreover, scaling in vertical dimension does not have the same limitations as scaling in the X and Y axes do. Because the cost of a semiconductor is still mostly determined by the die area and not by the height, there is no need to cram cells very close to each other. As a result, there is very little interference between the cells even in the vertical direction. Also, the usage of high-K dielectrics means that the control gate does not have to wrap around the charge trap. The result is that there is a hefty barrier of silicon dioxide (which is an insulator) between each cell, which is far more insulating than the rather thin ONO layer in 2D NAND. Unfortunately, I do not know what is the exact distance between each cell in the vertical dimension but I think it is safe to assume that it is noticeably more than the ~20nm in 2D NAND since there is no need for aggressive vertical scaling. 

As for how far Samsung believes their V-NAND can scale, their roadmap shows a 1Tbit die planned for 2017. That is very aggressive because it essentially implies that the die capacity will double every year (256Gbit next year, 512Gbit in 2016 and finally 1Tbit in 2017). The most interesting part is that Samsung is confident that they can do this simply by increasing the layer count, meaning that the process node will stay at 40nm. 

3D NAND: How It Works 3D NAND In Numbers: Is It Economical?
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  • Krakadoom - Saturday, September 27, 2014 - link

    I bought the 850 Pro 500 GB version. The transfer speeds are around (and just under) 400 MB/s and the IOPS are always around 55-60k. Not impressed - considering returning it just due to the huge gap between the rated specs and actual performance. (Of course Samsung Magician over-reports the transfer speed by quite a large margin).
  • stealth_lee - Wednesday, October 1, 2014 - link

    Someone just tipped me that V-NAND in Samsung 850 Pro is actually TLC not MLC.
    The first reason is the 86Gbit/die number is odd, if 850 Pro uses a TLC 128Gbit/die and emulates it to MLC then it would be 86Gbit/die, the numbers fit well.
    The second reason is Chipworks confirmed it in the die shots:
    http://bit.ly/YTVm9Z
    http://bit.ly/1uByKcm

    I'm just the messenger here, I'm not expert.
    So...I was wodering is it possible to hack Samsung 850 Pro to get extra storage space in TLC?
  • wcatlan - Saturday, October 25, 2014 - link

    Why isn't the lack of power loss protection a showstopper for any of these drives? I love the speed and reliability benefits under normal operation, but how can anyone get excited about a drive that can get corrupted in an instant due to power loss or computer freeze, where a hard shutdown is required? Seems that these drives are more prone to massive data issues much more than HDDs under the same power fault conditions. I keep looking for a good answer, but it seems smart people are willing to look past this seemingly fatal Achilles heal. Not sure what I might be missing. Any thoughts?
  • futurefilm - Monday, December 1, 2014 - link

    Today, Cyber Monday deals on Amazon, the 850 Pro 256 is going for $150. The 128 for $100. Get it now while it's hot.
  • saagar - Thursday, January 22, 2015 - link

    Dear Kristian Vättö,
    Fantastic review of the drives and the technology behind it. This is what readers like me expect to see on Anandtech. Thanks for breaking it down. Keep up the good work!
  • gsuburban - Wednesday, April 8, 2015 - link

    As of April 8, 2015, the 850 Pro 256GB SSD can be had for about $144 if you look hard enough.
  • rockfella79 - Saturday, June 27, 2015 - link

    I love my 850 Pro 128 GB SSD :)
  • KDT - Thursday, March 24, 2016 - link

    Please update the endurance to 300TBW for 1TB model. This was my basis for buying this SSD. This is 2nd to Crucial MX200 (320TBW on 1TB model) in terms of endurance - for client/consumer SSDs.
  • BimmerInd - Sunday, June 26, 2016 - link

    Samsung is using 40nm over Micron's 16nm. Doing the math implies that for every 2.5 16nm Micron nodes in planar section, Samsung only does 1 40nm node. If we scale vertically to 32 layers, then Micron (or others for that matter) still do only 2.5 nodes for every 32 nodes of Samsung. Which means for every 16nm node, Samsung provides 12.8 nodes. Meaning the density scaling factor for every 32 layer increments is a multiple of 12.8. Assuming the current die size for 32 layers to be 128Gbit, then the density advantage for 256Gbit is 12.8x2 times, 512Gbit is 12.8x4 times and for 1Tbit in 2017 should be 12.8x8 times for 256 layers of nodes stacked on top of each other. So the density advantage is approximately 102.4% (theoretically). Samsung can theoretically produce a 1Tbit die at a cost advantage/space advantage of nearly 100 times compared to planar and manufacturers. It is almost like you are able to earn 100 times the profit for the same die provided the cost per bit is scaled along without passing on the price advantage to the end users until other players enter 3D market.

    The same is the case with Intel's 3D Cross Point Technology. They are having a new tech in their hands that is faster than NAND and closer to DRAM. So they are also planning to price it exactly between NAND and DRAM. We are already paying high costs to shift from platters to NAND and are going to pay even more to make a shift from NAND to 3D xPoint. I just wish I can jump a few years to the future, grab a high capacity NAND/xPoint drive for cheap and come back to the present and use it. Sigh !
  • BimmerInd - Sunday, June 26, 2016 - link

    By the way this is just a rough calculation and is not to be taken literally.

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