Haswell's Wide Execution Engine

Conroe introduced the six execution ports that we've seen used all the way up to Ivy Bridge. Sandy Bridge saw significant changes to the execution engine to enable 256-bit AVX operations but without increasing the back end width. Haswell does a lot here.

Just as before, I put together a few diagrams that highlight the major differences throughout the past three generations for the execution engine.


The reorder buffer is one giant tracking structure for all of the micro-ops that are in various stages of execution. The size of this buffer is directly impacted by the accuracy of the branch predictor as that will determine how many instructions can be kept in flight at a given time.

The reservation station holds micro-ops as they wait for the data they need to begin execution. Both of these structures grow by low double-digit percentages in Haswell.

Simply being able to pick from more instructions to execute in parallel is one thing, we haven't seen an increase in the number of parallel execution ports since Conroe. Haswell changes that.

From Conroe to Ivy Bridge, Intel's Core micro-architecture has supported the execution of up to six micro-ops in parallel. While there are more than six execution units in the system, there are only six ports to stacks of execution units. Three ports are used for memory operations (loads/stores) while three are on math duty. Over the years Intel has added additional types and widths of execution units (e.g. Sandy Bridge added 256-bit AVX operations) but it hasn't strayed from the 6 port architecture.

Haswell finally adds two more execution ports, one for integer math and branches (port 6) and one for store address calculation (port 7). Including both additional compute and memory hardware is a balanced decision on Intel's part.

The extra ALU and port does one of two things: either improve performance for integer heavy code, or allow integer work to continue while FP math occupies ports 0 and 1. Remember that Haswell, like its predecessors, is an SMT design meaning each core will see instructions from up to two threads at the same time. Although a single app is unlikely to mix heavy vector FP and integer code, it's quite possible that two applications running at the same time may produce such varied instructions. Having more integer ALUs is never a bad thing.

Also using port 6 is another unit that can handle x86 branch instructions. Branch heavy code can now enjoy two independent branch units, or if port 0 is occupied with other math the machine can still execute branches on port 6. Haswell moved the original Core branch unit from port 5 over to port 0, the most capable port in the system, so a branch unit on a lightly populated port makes helps ensure there's no performance regression as a result of the change.

Sandy Bridge made ports 2 & 3 equal class citizens, with both capable of being used for load or store address calculation. In the past you could only do loads on port 2 and store addresses on port 3. Sandy Bridge's flexibility did a lot for load heavy code, which is quite common. Haswell's dedicated store address port should help in mixed workloads with lots of loads and stores.

The other major addition to the execution engine is support for Intel's AVX2 instructions, including FMA (Fused Multiply-Add). Ports 0 & 1 now include newly designed 256-bit FMA units. As each FMA operation is effectively two floating point operations, these two units double the peak floating point throughput of Haswell compared to Sandy/Ivy Bridge. A side effect of the FMA units is that you now get two ports worth of FP multiply units, which can be a big boon to legacy FP code.

Fused Multiply-Add operations are incredibly handy in all sorts of media processing and 3D work. Rather than having to independently multiply and add values, being able to execute both in tandem via a single execution port increases the effective execution width of the machine. Note that a single FMA operation takes 5 cycles in Haswell, which is the same latency as a FP multiply from Sandy/Ivy Bridge. In the previous generation a floating point multiply+add took 8 cycles, so there's a good latency improvement here as well as the throughput boost from having two FMA units.

Intel focused a lot on adding more execution horsepower in Haswell without creating a power burden for legacy use cases. All of the new units can be shut off when not in use. Furthermore, Intel went in and ensured that this applied to the older execution units as well: in Haswell if you're not doing work, you're not consuming power.

Prioritizing ILP Feeding the Beast: 2x Cache Bandwidth in Haswell
POST A COMMENT

245 Comments

View All Comments

  • Magik_Breezy - Sunday, October 14, 2012 - link

    Probably real customer support without paying an extra $200 Reply
  • Spunjji - Thursday, October 18, 2012 - link

    Yawn. Reply
  • Spunjji - Thursday, October 18, 2012 - link

    The bit that aggravates me the most is that even with this lavishing of review pages, the actual comparison of Apple products to competitors tends to lack (particularly with the Macbook article). This is understandable under some circumstances (iPhone battery life - new test, small selection of data points) but not for others. Reply
  • Arbee - Friday, October 5, 2012 - link

    I'm not really seeing any of that. AT's Android and Windows Phone reviews are just as in-depth and complementary where due as their Apple ones. AFAIK both Anand's and Brian's daily-driver phones aren't iPhones, even. They care about the tech, not who it comes from. It just happens that Apple is often the original source of new and interesting things in that space. At this exact moment they're the only people shipping something new and interesting. When the Nokia 920 launches, I'm confident Anand and Brian will be ready with a 15+ page review and discussion of anything novel on the podcast, and when Winter CES brings us Tegra 4 and other Android news, I expect to see eye-glazing levels of detail here at AT.

    (As an aside, I smiled at how closely DPReview's discussion of the alleged "purple haze" problem tracked Brian's rant on the podcast - clearly both writers know what they're talking about, which can be a rare quantity in tech journalism).
    Reply
  • VivekGowri - Saturday, October 6, 2012 - link

    I think Anand's daily driver is an iPhone, but he frequently carries the latest Android/WP device on the side. Brian and myself end up daily driving like a half dozen phones a month, depending on what shows up at our doorstep. Reply
  • Zink - Saturday, October 6, 2012 - link

    "iPad 3 form factor" was used because all of the other tablets have 25Wh batteries and draw about 5W max. The A5X iPad and it's giant 42.5Wh battery on the other hand can put out over 10W of heat which is the power envelope where Intel might target a Haswell SOC. Reply
  • amdwilliam1985 - Monday, October 8, 2012 - link

    I totally agree with you on the Apple part. That's the biggest pullback on reading Anand writings. Too much Apple praising.

    I used to be an Apple fan, but recently they're becoming the biggest jerks in the technology industry. The human/ethical part of in me hates them so much, that I won't buy anything that has a Apple logo on it.

    I gave away my iPad 2, switched to Samsung Galaxy S phones, and using my HP windows 7 laptop over the 2011 MBA.

    -say NO to bully, say NO to Apple.
    Reply
  • xaml - Thursday, May 23, 2013 - link

    Number of problems solved with this approach: NO. Reply
  • dartox - Tuesday, November 27, 2012 - link

    Probably because most people know about how large an iPad is - if he said "tablet" form factor that's ambigious.. and if he said "Motorola XOOM" form factor not as many people are familiar with the size. Reply
  • Paer0 - Friday, October 5, 2012 - link

    Yes... Macs are well engineered and deliver a solid performance across board. Reply

Log in

Don't have an account? Sign up now