Weaknesses of TLC: One Degree Worse than MLC

In a perfect world, increasing the number of bits per cell sounds like a very easy way to increase capacities while keeping the prices down. So, why not put a thousand bits inside every cell? Unfortunately, there's a downside to storing more bits per cell.

Fundamentally, TLC shares the same problems as MLC when compared to SLC, but takes things one step further. Now that there are eight voltage levels to check, random reads will take more time: 100µs for TLC. That's four times longer than what it takes SLC to random read one bit, and twice as long as what it takes for MLC to complete the same task. Programming will also take longer, but unfortunately we don't have any figures for TLC yet.

Bits per Cell 1 2 3
Random Read 25 µs 50 µs 100 µs
Erase 2ms per block 2ms per block ?
Programming 250 µs 900 µs ?

On top of the decrease in performance, TLC also has worse endurance than MLC and SLC. Precise P/E cycle figures are not yet known, but we are most likely looking at around 1000 cycles. Hynix has a brief product sheet for their 48nm TLC flash, which has 2500 P/E cycles. At least in MLC flash, the move to 3Xnm halved the P/E cycles so we would be looking at 1250 cycles. 2Xnm brought even fewer cycles, roughly 3,000, and with same math we get 750 cycles for 2Xnm TLC. X-bit labs reported 1,000 cycles for TLC, which sounds fair. It's also good to keep in mind that endurance can vary depending on the manufacturer and maturity of the process. For example the first 25nm NANDs were good for only ~1,000 cycles, whereas today's chips should last for over 3,000 cycles.

  5Xnm 3Xnm 2Xnm
SLC 100,000



MLC 10,000 5,000 3,000
TLC 2,500 1,250


But why does NAND with more bits degrade quicker? The reason lies in the physics of silicon. To understand this, we need to take a look at our beloved Mr. N-channel MOSFET again.

When you program a cell, you are placing a voltage on the control gate, while source and drain regions are held at 0V. The voltage forms an electric field, which allows electrons to tunnel through the silicon oxide barrier from the N-channel to the floating gate. This process is called tunneling. The silicon oxide acts as an insulator and will not allow electrons to enter or escape the floating gate unless an electrical field is formed. To erase a cell, you apply voltage on the silicon substrate (P-well in the picture) and keep control gate voltage at zero. An electric field will be formed which allows the electrons to get through the silicon oxide barrier. This is why NAND flash needs to be erased before it can be re-programmed: you need to get rid of the old electrons (i.e. old data) before you can apply new electrons (i.e. new data).

But what does this have to do with SLC, MLC and TLC? The actual MOSFET is exactly the same in all three cases, but take a look at the table below.

SLC "0" High Voltage
"1" Low Voltage
MLC "00" High Voltage
"01" Med-High Voltage
"10" Med-Low Voltage
"11" Low Voltage
TLC "000" Highest Voltage
"001" High Voltage
"010" Med-High Voltage
"100" High-Medium Voltage
"011" Low-Medium Voltage
"101" Med-Low Voltage
"110" Low Voltage
"111" Lowest Voltage




SLC only has two program states, "0" and "1". Hence either a high or low voltage is required. When the amount of bits goes up, you need more voltage stages. With MLC, there are four states, and eight states with TLC. The problem is that the silicon oxide layer is only about 10nm thick and it's not immortal; it wears out every time it's used in the tunneling process. When the silicon oxide layer wears out, the atomic bonds break and during the tunneling process, some electrons may get trapped inside the silicon oxide. This builds up negative charge in the silicon oxide, which negates some of the the control gate voltage.

At first, erasing becomes slower because higher voltages need to be applied (and for a longer time) before the right voltage is found. Higher voltage causes more stress on the oxide, wearing it out even more. Eventually, erasing will take so long that the block has to be retired to maintain the performance. There is a side effect, though. Programming will be faster because there is already some voltage in the cell due to the electron trapping. However, the time won because of that is much smaller than the time it takes to erase the cell when more voltage pulses are required to erase the cell. That's why the block has to be retired when the wear level reaches a certain point.

Here comes the differerence between SLC, MLC and TLC. The fewer bits you have per cell, the more voltage room you have. In other words, SLC can tolerate more changes in the voltage states because it has only two states. In TLC, there are eight, so the margin for errors is a lot smaller.

Lets assume that we have an SLC NAND that takes voltage between 0V and 14V. To program the cell to "1", a voltage between 4V and 5V needs to be applied. Likewise, you need a voltage from 9V to 10V to program the cell to "0". In this scenario, there is 4V of "spare" voltage between the states. If we apply this example to MLC NAND, the spare voltage will be cut to half, 2V. With TLC, that spare value is only 0.67V if we use the same 1V per voltage state ideaology.

However, when the oxide wears out and a higher voltage is needed, the programming voltages go up. To use the SLC example above, you would now need a voltage between 4V and 6V to program the cell to "0". That means a 1V loss in the spare voltage. And here comes the difference. Since SLC has more spare voltage between the states, it can tolerate a higher voltage change until the erase will be so slow that the block needs to be retired. This is why SLC has a substantially higher P/E cycle count; you can erase and reprogram the cell more times. Likewise, TLC tolerates the least change in voltage states, so it has the lowest amount of P/E cycles.

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  • Kristian Vättö - Saturday, February 25, 2012 - link

    I just used the names that manufacturers use. If you look at e.g. Micron's part catalog (linked below), they use SLC, MLC and TLC. I agree that the naming is misleading because MLC should refer to any NAND with multiple bits per cell. TLC is sometimes called as 3-bit-per-cell MLC or just MLC-3 but the TLC name is gaining more momentum all the time.

  • foolsgambit11 - Sunday, February 26, 2012 - link

    Thanks. Reply
  • Taracta - Sunday, February 26, 2012 - link

    Shouldn't the TLC be 64Gb? It holds twice as much information as MLC as MLC hold twice as much as SLC. Each increment in bits doubles the information stored as stated in the article, SLC 2bits stored, MLC 4bits stored and TLC 8bits (1 BYTE) stored. Reply
  • Taracta - Sunday, February 26, 2012 - link

    You are dealing with base-2 values. Each additional bit doubles the amount of data that is stored. You even have the correct values in the begining of the article. SLC stores 2 bitsof information 0 and 1, MLC stores 4 bits of information 00, 01, 10, 11 and TLC store 8 bits (1 BYTE) of information 000, 001, 010, 011, 100, 101, 110, 111 yet further down in the article you are stating that TLC stores only a third more that of SLC. You are confusing the bit place holder with the actual information that is being stored. TLC has an additional bit place holder compared to MLC which has an additional bit place holder compared to SLC. Each bit place holder increases the storage capability by a power of two (2). Reply
  • Kristian Vättö - Sunday, February 26, 2012 - link

    SLC stores 1-bit per cell/transistor and the value can be either 0 or 1. It cannot be 0 and 1 at the same time.

    MLC stores 2-bits cell. This means the value can be either 00, 01, 10, or 11. However, it can only be programmed to have one value. One MLC cell cannot store e.g. 00 and 01 at the same time. One 0 or 1 is one bit of data, i.e. 00 is two bits of data. I don't know how you are coming up with four bits, maybe you are mixing it with the voltage states (each value needs its own voltage state so when you program a cell to e.g. 00, it will be read as 00).

    TLC just increases the bits per cell to three which means the possible values are 000, 001, 010, 100, 011, 110 101, and 111. Again, eight voltage states and three bits per cell.

    Each additional bit per cell increases the voltage states by a power of 2 (in math terms: 2^n, where n is the amount of bits per cell). Amount of bits per cell is just n, it's not a power of two. MLC is 2*1=2, and 2 is 100% bigger than 1. TLC is 3*1=3. and 3 is 200% bigger than 1 but only 50% more than 2.
  • Taracta - Sunday, February 26, 2012 - link

    Ok let me make it simple because I still think you are confusing yourself.

    SLC possible values are 0 or 1 which is equal to 2 values with is 2^1

    MLC possible values are 0, 1, 10 or 11 which is equal to 4 values which is 2^2

    TLC possible values are 0, 1, 10, 11, 100, 101, 110 or 111 which is equal to 8 values which is 2^3

    Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)

    Is this right?
  • KitsuneKnight - Sunday, February 26, 2012 - link

    He's not confusing himself, you're confused about binary numbers and bits.

    "Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)"

    Don't confuse the amount of bits of storage, with the maximum value it can hold.

    Since you seem to be getting confused with binary numbers, lets work with decimals numbers for a bit.

    Lets say an 'SLC' can represent the values 0-9. An MLC can represent the values 0-9, 0-9 or 00-99 (that's two sets of 0-9 next to each other!). A TLC can represent the values 0-9,0-9,0-9 or 000-999. It should be patently obvious that an TLC doesn't have 100 times the capcity of an SLC cell! A /single one/ can hold a VALUE 100 times, but, 3 SLCs next to each other could hold the same value.

    A linear growth of bits results in an /exponential/ growth of the value those bits, when combined, can represent. It doesn't matter if all those bits are from a single cell, or X number of cells. How you get bits doesn't matter.
  • Taracta - Monday, February 27, 2012 - link


    Did some research to see where you were coming from with the data you presented.


    gives some insight on TLC block sizes and why is doesn't follow the actual size of a TLC cell. Basically some pages and not use in TLC block configurations. Strangely the amount of pages in a TLC block is more than double that of a MLC block!

    I leave it up to you to clarify the article as it is somewhat confusing and needs some explanation of the differences between the cell, page and block sizes for TLC.
  • Kristian Vättö - Monday, February 27, 2012 - link

    Actually, TLC block size does (or at least should) follow the bits-per-cell idea. 25nm IMFT MLC NAND brought us 8KB pages and 256 pages per block. According to your link, TLC has 384 pages per block (i.e. 3*128 which means 128 pages per bit). MLC is now using that same 128 pages per bit idea (before it was 64 pages per bit).

    It's possible that TLC moved to a bigger block size before MLC and SLC because that lowers the cost and ultimately TLC is all about cost. There is need for less peripheral circuits between the blocks, which makes the die smaller and hence reduces production costs.


    I don't know what this has to do with your original point about the article being wrong, though. Of course, I'm happy to answer any questions regarding TLC, or at least give it a try (I haven't studied NAND technology in a university so e.g. that math stuff in your link is over my head).
  • mdshann - Monday, March 05, 2012 - link

    I haven't seen a 500 GB hard drive for anywhere near $50 in about 6 months now... where are you getting these drives? Right now the cheapest 500 GB drive on newegg.com is $84.99 and it's a bare Hitachi. Reply

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