Weaknesses of TLC: One Degree Worse than MLC

In a perfect world, increasing the number of bits per cell sounds like a very easy way to increase capacities while keeping the prices down. So, why not put a thousand bits inside every cell? Unfortunately, there's a downside to storing more bits per cell.

Fundamentally, TLC shares the same problems as MLC when compared to SLC, but takes things one step further. Now that there are eight voltage levels to check, random reads will take more time: 100µs for TLC. That's four times longer than what it takes SLC to random read one bit, and twice as long as what it takes for MLC to complete the same task. Programming will also take longer, but unfortunately we don't have any figures for TLC yet.

Bits per Cell 1 2 3
Random Read 25 µs 50 µs 100 µs
Erase 2ms per block 2ms per block ?
Programming 250 µs 900 µs ?

On top of the decrease in performance, TLC also has worse endurance than MLC and SLC. Precise P/E cycle figures are not yet known, but we are most likely looking at around 1000 cycles. Hynix has a brief product sheet for their 48nm TLC flash, which has 2500 P/E cycles. At least in MLC flash, the move to 3Xnm halved the P/E cycles so we would be looking at 1250 cycles. 2Xnm brought even fewer cycles, roughly 3,000, and with same math we get 750 cycles for 2Xnm TLC. X-bit labs reported 1,000 cycles for TLC, which sounds fair. It's also good to keep in mind that endurance can vary depending on the manufacturer and maturity of the process. For example the first 25nm NANDs were good for only ~1,000 cycles, whereas today's chips should last for over 3,000 cycles.

  5Xnm 3Xnm 2Xnm
SLC 100,000



MLC 10,000 5,000 3,000
TLC 2,500 1,250


But why does NAND with more bits degrade quicker? The reason lies in the physics of silicon. To understand this, we need to take a look at our beloved Mr. N-channel MOSFET again.

When you program a cell, you are placing a voltage on the control gate, while source and drain regions are held at 0V. The voltage forms an electric field, which allows electrons to tunnel through the silicon oxide barrier from the N-channel to the floating gate. This process is called tunneling. The silicon oxide acts as an insulator and will not allow electrons to enter or escape the floating gate unless an electrical field is formed. To erase a cell, you apply voltage on the silicon substrate (P-well in the picture) and keep control gate voltage at zero. An electric field will be formed which allows the electrons to get through the silicon oxide barrier. This is why NAND flash needs to be erased before it can be re-programmed: you need to get rid of the old electrons (i.e. old data) before you can apply new electrons (i.e. new data).

But what does this have to do with SLC, MLC and TLC? The actual MOSFET is exactly the same in all three cases, but take a look at the table below.

SLC "0" High Voltage
"1" Low Voltage
MLC "00" High Voltage
"01" Med-High Voltage
"10" Med-Low Voltage
"11" Low Voltage
TLC "000" Highest Voltage
"001" High Voltage
"010" Med-High Voltage
"100" High-Medium Voltage
"011" Low-Medium Voltage
"101" Med-Low Voltage
"110" Low Voltage
"111" Lowest Voltage




SLC only has two program states, "0" and "1". Hence either a high or low voltage is required. When the amount of bits goes up, you need more voltage stages. With MLC, there are four states, and eight states with TLC. The problem is that the silicon oxide layer is only about 10nm thick and it's not immortal; it wears out every time it's used in the tunneling process. When the silicon oxide layer wears out, the atomic bonds break and during the tunneling process, some electrons may get trapped inside the silicon oxide. This builds up negative charge in the silicon oxide, which negates some of the the control gate voltage.

At first, erasing becomes slower because higher voltages need to be applied (and for a longer time) before the right voltage is found. Higher voltage causes more stress on the oxide, wearing it out even more. Eventually, erasing will take so long that the block has to be retired to maintain the performance. There is a side effect, though. Programming will be faster because there is already some voltage in the cell due to the electron trapping. However, the time won because of that is much smaller than the time it takes to erase the cell when more voltage pulses are required to erase the cell. That's why the block has to be retired when the wear level reaches a certain point.

Here comes the differerence between SLC, MLC and TLC. The fewer bits you have per cell, the more voltage room you have. In other words, SLC can tolerate more changes in the voltage states because it has only two states. In TLC, there are eight, so the margin for errors is a lot smaller.

Lets assume that we have an SLC NAND that takes voltage between 0V and 14V. To program the cell to "1", a voltage between 4V and 5V needs to be applied. Likewise, you need a voltage from 9V to 10V to program the cell to "0". In this scenario, there is 4V of "spare" voltage between the states. If we apply this example to MLC NAND, the spare voltage will be cut to half, 2V. With TLC, that spare value is only 0.67V if we use the same 1V per voltage state ideaology.

However, when the oxide wears out and a higher voltage is needed, the programming voltages go up. To use the SLC example above, you would now need a voltage between 4V and 6V to program the cell to "0". That means a 1V loss in the spare voltage. And here comes the difference. Since SLC has more spare voltage between the states, it can tolerate a higher voltage change until the erase will be so slow that the block needs to be retired. This is why SLC has a substantially higher P/E cycle count; you can erase and reprogram the cell more times. Likewise, TLC tolerates the least change in voltage states, so it has the lowest amount of P/E cycles.

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View All Comments

  • Kristian Vättö - Friday, February 24, 2012 - link

    There is HET-MLC (or usually known as eMLC) which is MLC NAND aimed for enterprises. It stores two bits per cell like normal MLC but its P/E cycle rate is much higher (IIRC something like 50,000). Unfortunately I don't know how it really differs from regular MLC but it's a lot more expensive than regular MLC.

    SLC, MLC and TLC simply refer to the amount of bits per cell, there is no 1-bit-per-cell MLC as MLC alone means multi-level-cell, and one isn't multi ;-)
  • ckryan - Friday, February 24, 2012 - link

    I wasn't aware that this was going on until I read the UCSD paper "the Bleak Future of NAND Flash Memory. Somehow, you can use MLC to store just one bit, and it gets similar, but not identical, performance to SLC.


    This was the study that was said to cast doubt on the ability to scale NAND effectively past 2024.

    They tested this particular MLC-1 setup. Even if you discard half the capacity of MLC, it's still cheaper than SLC bit for bit.

    HET-MLC and eMLC really are just highly binned MLC NAND. Toshiba gives it's eMLC 10kPE cycles. But enterprise drives only have to retain data for 3 months at MWI=0, so some of this extra endurance comes from that.
  • Kristian Vättö - Friday, February 24, 2012 - link

    Ooh, interesting, thanks for the link! I was sure that you had mixed up eMLC and MLC because MLC-1 doesn't make much sense, at least not without further explanation.

    Does the study say how much cheaper MLC-1 is when compared with SLC (I don't have time to read it thoroughly now, but will do tomorrow)? Like I said in the article, MLC is the highest volume product and gets the new process nodes first, so that might be the reason why MLC-1 is a bit cheaper than SLC. Shouldn't be much, though.
  • This Guy - Friday, February 24, 2012 - link

    There is a better tech in the wings anyway. Memristors:


    Memristors will create a giant performance boost. Their low latency and high density will allow for the replacement of HDDs and RAM. And this could be a second generation product out in three years.

    If the worst memory latency was ~20ns instead of ~50µs (SSD) or ~20ms(HDD), cache misses would stop being a problem. Old, simple CPU architectures could be reproduced (with I/O upgrades) and bundled with memristor storage and compete with current designs.

    In 10 years we could see CPUs replaced with multi-chip modules containing large memristor banks, ALU's with a far larger variety of operations (including GPGPU operations) and the system's I/O. No cache. No registers. No stalls.
  • jjj - Saturday, February 25, 2012 - link

    Those are dreams for now.
    Anyway Sandisk/Toshiba sell a lot of TLC already, in certain products.They even had 4 bits per cell but that's not being produced anymore.As for the future they got 2 things, BiCS and 3D ReRAM. We'll see soon enough if any of those make it to market .
  • rpmurray - Thursday, February 23, 2012 - link

    While cheaper is sure tempting I'm not making the move until I stop seeing so many users giving one-star ratings on Newegg when their nice new SSD bricks itself anywhere between one day and three months. Reply
  • jdjbuffalo - Thursday, February 23, 2012 - link

    As opposed to all the people who get new 2TB hard drives that fail in the first day? Reply
  • pc_void - Thursday, February 23, 2012 - link

    So true. It is said that if it lasts for 3 months then it will probably last for years - talking about hard disk drives or anything for that matter.

    In my opinion, people brick ssd drives because they are not dummy proof.
  • pc_void - Thursday, February 23, 2012 - link

    Except for the exceptions. Reply
  • Folterknecht - Thursday, February 23, 2012 - link

    The same goes for many other components - hdds, gpu, mobo ...

    And often enough there is either a crappy PSU or RAM involved doesnt work as it should. I dont really trust those "user reviews" on sites like Newegg, to many people writing there that have no idea what they are talking about.

    Of course firmware issues exist, not denying that, but thats no reason pass the best possible upgrade for your pc (in most cases).

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