Core-to-Core Latency

As the core count of modern CPUs is growing, we are reaching a time when the time to access each core from a different core is no longer a constant. Even before the advent of heterogeneous SoC designs, processors built on large rings or meshes can have different latencies to access the nearest core compared to the furthest core. This rings true especially in multi-socket server environments.

But modern CPUs, even desktop and consumer CPUs, can have variable access latency to get to another core. For example, in the first generation Threadripper CPUs, we had four chips on the package, each with 8 threads, and each with a different core-to-core latency depending on if it was on-die or off-die. This gets more complex with products like Lakefield, which has two different communication buses depending on which core is talking to which.

If you are a regular reader of AnandTech’s CPU reviews, you will recognize our Core-to-Core latency test. It’s a great way to show exactly how groups of cores are laid out on the silicon. This is a custom in-house test, and we know there are competing tests out there, but we feel ours is the most accurate to how quick an access between two cores can happen.


Click to enlarge (lots of cores and threads = lots of core pairings)

Comparing core to core latencies from Zen 4 (7950X) and Zen 3 (5950X), both are using a two CCX 8-core chiplet design, which is a marked improvement over the four CCX 16-core design featured on the Zen 2 microarchitecture, the Ryzen 9 3950X. The inter-core latencies within the L3 cache range from between 15 ns and 19 ns. The inter-core latencies between different cores within different parts of the CCD show a larger latency penalty of up to 79.5 ns, which is something AMD should work on going forward, but it's an overall improvement in cross CCX latencies compared to Zen 3. Any gain is still a gain.

Even though AMD has opted for a newer and more 'efficient' IOD which is based on TSMC's 6 nm node. It is around the same size physically as the previous AMD IOD on Zen 3 manufactured on GlobalFoundries 12 nm node, but with a much larger transistor count. Within the IOD is the newly integrated RDNA 2 graphics, although this isn't typical iGPU in the sense that an APU is. A lot of the room on the IOD is made up of the DDR5 memory controller or IMC, as well as the chips PCIe 5.0 lanes, and of course, connects to the logic through its primary interconnect named Infinity Fabric. All of these variables play a part on power, latency, and operation.


AMD Ryzen 9 5950X Core-to-Core Latency results

It's actually astounding how similar the latency performance of the Ryzen 9 7950X (Zen 4) is when compared directly to the Ryzen 9 5950X (Zen 3), despite being on the new 5 nm TSMC manufacturing process. Even with a change of IOD, but with the same interconnect, the inter-core latencies within the Ryzen 9 7950X are great in terms of cores within the same core complex; latency does degrade when pairing up with a core in another chiplet, but this works and AMD's Ryzen 5000 series proved that the overall penalty performance is negatable.

Test Bed and Setup SPEC2017 Single-Threaded Results
POST A COMMENT

205 Comments

View All Comments

  • Iketh - Thursday, October 6, 2022 - link

    why are you giving so much credit to ddr5? moving to new memory has always given very small gains (if any) in the beginning

    tjunction is an arbitrary number set by AMD, so using that as an argument is irrational
    Reply
  • xol - Tuesday, September 27, 2022 - link

    ..but my main criticism was of the article - eg phrases like " increase the overall TDP ... without too much penalty" doesn't really make any sense - increase TDP is the penalty

    But much of the article is written as if letting TDP go *much* higher is some sort of gift from AMD -eg the examples I gave

    The article is full of nothin-burgers like this statement :
    " We feel that the higher all-core frequencies under maximum load, 95°C is a sufficient level of heat for what is on offer when it comes to overall performance"
    Reply
  • kwrzesien - Monday, September 26, 2022 - link

    Whomever was the last to edit the front page needs to disable the trackpad and clean their mouse ball! 🤣 Reply
  • Threska - Monday, September 26, 2022 - link

    "But now with AMD’s modern RDNA 2 graphics architecture and TSMC fabrication process, AMD has finally seen the (ray traced) light, and is building a small GPU block into the IOD to offer integrated graphics throughout the Ryzen 7000 product stack."

    I see things like SAM and HSA being a future trend.

    https://www.electronicdesign.com/technologies/micr...
    Reply
  • erotomania - Wednesday, September 28, 2022 - link

    Yes, AMD thought so too, in 2012...

    https://www.tomshardware.com/reviews/fusion-hsa-op...

    and in 2014 here at AT...

    https://www.anandtech.com/show/7677/amd-kaveri-rev...

    Hopefully this time!
    Reply
  • nandnandnand - Monday, September 26, 2022 - link

    It seems that going up by 1 GHz didn't help it that much in gaming benchmarks.

    Meanwhile, the 65W results show that any Zen 4 and later APUs are going to be absurdly powerful. Especially Dragon Range.
    Reply
  • Josh128 - Monday, September 26, 2022 - link

    Any way you guys can add the single core ECO mode results to the conclusion page or to the R23 results on its respective page? Reply
  • donquixote42 - Monday, September 26, 2022 - link

    Single threaded workload would not use more than 65W anyway. So performance should be the same in ECO and non-ECO mode. Reply
  • Josh128 - Monday, September 26, 2022 - link

    Still using a 2080Ti for the games testing is not good. Most certainly many of these results are GPU bound. Reply
  • snowdrop - Monday, September 26, 2022 - link

    No power consumption numbers? Will the article be updated with these when they're ready? Reply

Log in

Don't have an account? Sign up now