Core-to-Core Latency

As the core count of modern CPUs is growing, we are reaching a time when the time to access each core from a different core is no longer a constant. Even before the advent of heterogeneous SoC designs, processors built on large rings or meshes can have different latencies to access the nearest core compared to the furthest core. This rings true especially in multi-socket server environments.

But modern CPUs, even desktop and consumer CPUs, can have variable access latency to get to another core. For example, in the first generation Threadripper CPUs, we had four chips on the package, each with 8 threads, and each with a different core-to-core latency depending on if it was on-die or off-die. This gets more complex with products like Lakefield, which has two different communication buses depending on which core is talking to which.

If you are a regular reader of AnandTech’s CPU reviews, you will recognize our Core-to-Core latency test. It’s a great way to show exactly how groups of cores are laid out on the silicon. This is a custom in-house test, and we know there are competing tests out there, but we feel ours is the most accurate to how quick an access between two cores can happen.


Click to enlarge (lots of cores and threads = lots of core pairings)

Comparing core to core latencies from Zen 4 (7950X) and Zen 3 (5950X), both are using a two CCX 8-core chiplet design, which is a marked improvement over the four CCX 16-core design featured on the Zen 2 microarchitecture, the Ryzen 9 3950X. The inter-core latencies within the L3 cache range from between 15 ns and 19 ns. The inter-core latencies between different cores within different parts of the CCD show a larger latency penalty of up to 79.5 ns, which is something AMD should work on going forward, but it's an overall improvement in cross CCX latencies compared to Zen 3. Any gain is still a gain.

Even though AMD has opted for a newer and more 'efficient' IOD which is based on TSMC's 6 nm node. It is around the same size physically as the previous AMD IOD on Zen 3 manufactured on GlobalFoundries 12 nm node, but with a much larger transistor count. Within the IOD is the newly integrated RDNA 2 graphics, although this isn't typical iGPU in the sense that an APU is. A lot of the room on the IOD is made up of the DDR5 memory controller or IMC, as well as the chips PCIe 5.0 lanes, and of course, connects to the logic through its primary interconnect named Infinity Fabric. All of these variables play a part on power, latency, and operation.


AMD Ryzen 9 5950X Core-to-Core Latency results

It's actually astounding how similar the latency performance of the Ryzen 9 7950X (Zen 4) is when compared directly to the Ryzen 9 5950X (Zen 3), despite being on the new 5 nm TSMC manufacturing process. Even with a change of IOD, but with the same interconnect, the inter-core latencies within the Ryzen 9 7950X are great in terms of cores within the same core complex; latency does degrade when pairing up with a core in another chiplet, but this works and AMD's Ryzen 5000 series proved that the overall penalty performance is negatable.

Test Bed and Setup SPEC2017 Single-Threaded Results
POST A COMMENT

205 Comments

View All Comments

  • linuxgeex - Monday, September 26, 2022 - link

    All Microsoft customers are QA testers, lol. That's always how it's been. Reply
  • Kangal - Tuesday, September 27, 2022 - link

    Isn't that what goes for Linux?
    The only difference is that you don't pay money, you just pay in time, effort, frustration, and your soul.
    Reply
  • Hifihedgehog - Tuesday, September 27, 2022 - link

    Exactly. And you compile your own kernel for 24 hours hoping it will finish successfully. Reply
  • at_clucks - Wednesday, October 19, 2022 - link

    Not if you use the latest Ryzen 9 7950X. You may still pray it's successful at the end but God will answer a lot faster :). Reply
  • elforeign - Monday, September 26, 2022 - link

    Ah yes, the capitalistic adage of less is more. I'm sorry you guys have to deal with this, as with anyone in the workforce, where the powers that be sit on their ass with their cushy millions and say workers can do less with more and pile on with disregard.

    On a further note, I have been coming to Anandtech since the mid 00's. While I can understand the expectation surrounding good grammar and flawless articles, some issues are bound to come up now and then. The vitriol you guys receive for some simple grammar or syntax mistake is crazy.
    Reply
  • rarson - Wednesday, September 28, 2022 - link

    "Ah yes, the capitalistic adage of less is more."

    This is not a thing.
    Reply
  • herozeros - Monday, September 26, 2022 - link

    Kind reply, thanks. Hope your week lets you catch up.

    No more copy editors?! I guess my blonde is all now truly grey . . . sigh
    Reply
  • Threska - Monday, September 26, 2022 - link

    Outsourced to AI. Reply
  • emn13 - Monday, September 26, 2022 - link

    I for one thoroughly enjoyed your article, and appreciate the technical content - a few editing nits don't detract from that.

    And hey, if I were to whine about embarrassing editing mistakes, rather than focusing on a long article written in limited time due to AMD's schedule, I'd poke fun at the 100 000 000 000 $ company's press slides touting their EXPO tech's openness in the form of public "doucments". 😀
    Reply
  • linuxgeex - Monday, September 26, 2022 - link

    So long as you're open to community feedback to correct hasty errors, there's no need for copy editors, and you can push your articles faster, which we'll all appreciate. Saying thanks is much more productive than making excuses. It shows that you appreciate your community. Reply

Log in

Don't have an account? Sign up now