Intel CPU Roadmap Update

We have a small update to the Intel desktop roadmap, and not much has really changed. Everything from our last update remains the same, and it's basically business as usual. So what's new? We'll start off with the most interesting area in our view, the dual core units. As usual, we'll highlight the updates and additions.

Intel Desktop Performance Roadmap
Processor Core Name Clock Speed Socket Launch Date
??? Conroe ??? ??? 2H'06
Pentium D >= 950 Presler ??? LGA 775 Q2'06
Pentium D 950 Presler 3.4 2x2MB LGA 775 Q1'06
Pentium D 940 Presler 3.2 2x2MB LGA 775 Q1'06
Pentium D 930 Presler 3.0 2x2MB LGA 775 Q1'06
Pentium D 920 Presler 2.8 2x2MB LGA 775 Q1'06

We already covered the arrival of the Presler Pentium D cores last month (and Smithfield has been available for a few months). The chips will be dual core 65nm parts with EM64T, VT, EIST, and XD. If you're not familiar with those acronyms, here's the recap:

  • EM64T adds 64-bit support and is the Intel equivalent of AMD64.
  • XD provides some protection against buffer overflow attacks, again matching up to AMD's NX (No-eXecute) technology.
  • VT stands for Virtualization Technology and provides hardware level support for running multiple OSes concurrently on a single computer.

As we mentioned in our recent AMD roadmap update, it was only possible to run multiple OSes concurrenty in the past through such third party tools as VMware, and the hardware support should increase the performance quite a bit. As with the other technologies mentioned, VT has an AMD counterpart, dubbed Pacifica. The remaining technology warrants further explanation.

EIST stands for Enhanced Intel Speedstep Technology, which allows the processors to throttle down to lower clock speeds and voltages when idle and thus conserve power. The version of EIST in the Presler core should be superior to that of the Smithfield core as it will also be available on the 2.8 GHz model. Current EIST on Pentium and Pentium D chips reduces the clock speed to 2.8 GHz, making it a useless feature for a chip that runs at 2.8 GHz by default. We don't have any specific details on the new EIST, but we hope that it will offer more benefits than a static clock speed and voltage reduction. Ideally, we'd like to see something like AMD's Cool and Quiet where all lower CPU multipliers are unlocked - that's what Intel has in their Pentium M chips as well. Overclockers in particular like to have such control; however, Intel may or may not offer that degree of tuning.

We have one new entry for a potentially faster Presler model: 960 running at 3.6 GHz is the most probable candidate, although whether or not Intel decides to release such a chip will depend on a variety of factors. The more interesting addition is Conroe, which will use Intel's next generation architecture. Details on what Conroe will bring to the table are scarce, but we would imagine that all the previously mentioned technologies will be present. The major change is that Conroe will not use the NetBurst architecture that has been used in the Pentium 4 (and derivatives) line.

For those that don't follow processors closely, here's a brief explanation on why this decision was made. The long pipeline of NetBurst has become a liability with clock speeds beyond 4 GHz producing a lot of heat. Increasing clock speeds have always created more heat, but now we're hitting the point where they begin to scale out of control. Rather than trying to find ways of dealing with 150W power levels (or perhaps even higher), Intel has designed a new architecture "from the ground up." Of course, they're not really starting over, as they'll be using elements of all of their previous designs, but Conroe will be enough of a change that it will have a new name.

Thinking About Conroe
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  • JarredWalton - Friday, August 12, 2005 - link

    Heheh... 45nm? Let us reach 65nm first. ;)

    The roadmaps don't typically go that far out. Once the transition to 65nm is complete, we'll probably start getting information on their 45nm transition. Rough guess would be that it will launch around 18 months after 65nm, so mid-2007 give or take.
  • nserra - Wednesday, August 17, 2005 - link

    65nm will put intel in line with what AMD have already achived with 90nm.
  • NFS4 - Wednesday, August 10, 2005 - link

    I can't wait for the Intel Cornrows :D
  • BitByBit - Thursday, August 11, 2005 - link

    I'm interested in what AMD's response to Conroe will be.
    If Conroe is indeed going to be a wide-issue, efficient design, then its average IPC should easily exceed that of the K8, while its longer pipeline (in comparison with K8/Dothan) will enable it to hit higher clock speeds. The lessons Intel learned with Netburst will likely compliment its Next Generation architecture nicely, such as the importance of good branch prediction, along with innovations such as Trace Cache.

    If we assume Conroe will be released at speeds in the lower 2Ghz range initially, then AMD should have time to hold out until it is ready to release K10.
    The question is: what will K10 bring us?
  • segagenesis - Friday, August 12, 2005 - link

    I would argue that AMD's response *was* the K8. It seems that Intel is playing catch up as far as architecture goes and were not going to see these new cpus for a long time still. As long as they dont come out and say "sorry, no more x86 even though the entire damn world still uses it".
  • nserra - Wednesday, August 17, 2005 - link

    Maybe the K8 on socket M2 will come with some surprises, that just the DDR2 support.
  • ZobarStyl - Thursday, August 11, 2005 - link

    Yeah, I'm more interested in what the K10 can do better that what Conroe finally just manages to get right. Here's hoping AMD has something more than just clockspeed and cache updates coming.
  • reactor - Friday, August 12, 2005 - link

    eliminate the southbridge? ;D
  • coldpower27 - Wednesday, August 10, 2005 - link

    Yeha I am really interested to see how this 4th architecture will relate to the other 3 Intel has.
  • Doormat - Wednesday, August 10, 2005 - link

    The real question is how much ILP can the chip squeeze out of the code (and compilers). If intel can get more ILP and non-dependant instructions dispatched to the execution units, then they'll be ahead. I just dont know that there is more to ILP to get out of current code with the technologies known about and used in today's processors. Otherwise, wider execution paths would help only if there was Hyperthreading (or some derivative) available to process two threads at once, and fill up all the execution units with instructions to perform.

    Otherwise you might as well just use the extra die space and go multicore or hybrid multicore (main cores plus specialized cores for TCP/IP offloading, encryption, etc).

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