Intel CPU Roadmap Update

We have a small update to the Intel desktop roadmap, and not much has really changed. Everything from our last update remains the same, and it's basically business as usual. So what's new? We'll start off with the most interesting area in our view, the dual core units. As usual, we'll highlight the updates and additions.

Intel Desktop Performance Roadmap
Processor Core Name Clock Speed Socket Launch Date
??? Conroe ??? ??? 2H'06
Pentium D >= 950 Presler ??? LGA 775 Q2'06
Pentium D 950 Presler 3.4 2x2MB LGA 775 Q1'06
Pentium D 940 Presler 3.2 2x2MB LGA 775 Q1'06
Pentium D 930 Presler 3.0 2x2MB LGA 775 Q1'06
Pentium D 920 Presler 2.8 2x2MB LGA 775 Q1'06

We already covered the arrival of the Presler Pentium D cores last month (and Smithfield has been available for a few months). The chips will be dual core 65nm parts with EM64T, VT, EIST, and XD. If you're not familiar with those acronyms, here's the recap:

  • EM64T adds 64-bit support and is the Intel equivalent of AMD64.
  • XD provides some protection against buffer overflow attacks, again matching up to AMD's NX (No-eXecute) technology.
  • VT stands for Virtualization Technology and provides hardware level support for running multiple OSes concurrently on a single computer.

As we mentioned in our recent AMD roadmap update, it was only possible to run multiple OSes concurrenty in the past through such third party tools as VMware, and the hardware support should increase the performance quite a bit. As with the other technologies mentioned, VT has an AMD counterpart, dubbed Pacifica. The remaining technology warrants further explanation.

EIST stands for Enhanced Intel Speedstep Technology, which allows the processors to throttle down to lower clock speeds and voltages when idle and thus conserve power. The version of EIST in the Presler core should be superior to that of the Smithfield core as it will also be available on the 2.8 GHz model. Current EIST on Pentium and Pentium D chips reduces the clock speed to 2.8 GHz, making it a useless feature for a chip that runs at 2.8 GHz by default. We don't have any specific details on the new EIST, but we hope that it will offer more benefits than a static clock speed and voltage reduction. Ideally, we'd like to see something like AMD's Cool and Quiet where all lower CPU multipliers are unlocked - that's what Intel has in their Pentium M chips as well. Overclockers in particular like to have such control; however, Intel may or may not offer that degree of tuning.

We have one new entry for a potentially faster Presler model: 960 running at 3.6 GHz is the most probable candidate, although whether or not Intel decides to release such a chip will depend on a variety of factors. The more interesting addition is Conroe, which will use Intel's next generation architecture. Details on what Conroe will bring to the table are scarce, but we would imagine that all the previously mentioned technologies will be present. The major change is that Conroe will not use the NetBurst architecture that has been used in the Pentium 4 (and derivatives) line.

For those that don't follow processors closely, here's a brief explanation on why this decision was made. The long pipeline of NetBurst has become a liability with clock speeds beyond 4 GHz producing a lot of heat. Increasing clock speeds have always created more heat, but now we're hitting the point where they begin to scale out of control. Rather than trying to find ways of dealing with 150W power levels (or perhaps even higher), Intel has designed a new architecture "from the ground up." Of course, they're not really starting over, as they'll be using elements of all of their previous designs, but Conroe will be enough of a change that it will have a new name.

Thinking About Conroe
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  • IntelUser2000 - Monday, August 22, 2005 - link

    First Itanium is 6-wide
    Itanium 2 is 6-wide

    Itanium 2 doesn't increase the issue rate, what Itanium 2 does is increase the possibility that IPC of 6 is possible by making better architecture.

    Brief overview of Itanium architecture: The CPU processes the EPIC instructions by using two bundles of 3 instructions each, therefore achieving IPC of 6. Each bundle can have a certain combination of different instructions.

    Main execution units in Itanium consists of 4 different kinds, that is Branch unit, Floating Point Unit, Memory Unit, Integer Unit. Memory and Integer unit can be considered in simple terms as ALU from what I understand.

    In one bundle, you can have certain combinations of those execution units. Examples may be: MMI(memory, memory, integer), MII, MIF, BBB, and such. Remember that each bundle can have that combinations, and there is like 26 combinations or so. That means if the second bundle can't have that combinations due to the lack of execution units, 6-wide isn't possible.

    Itanium had 2 M units, 2 I units, 2 FP units, 3 B units. So if the first bundle is MMI and the second bundle is MMI, it can't have 6-wide execution.

    According to the article I read, first Itanium can have in theory of ~3.8 IPC due to lack of execution units, and Itanium 2 have theoretical IPC of 5.6-5.7 due to more execution units, specifically 4 M units rather than 2 as in Itanium.


    There are two kind of ways to run 32-bit for Itanium. One way is the hardware emulator that's in all current Itanium chips. The 32-bit performance for first Itanium runs 32-bit x86 code as worse as 66MHz 486, or good as 200MHz Pentium MMX, when Itanium is running at 800MHz. Itanium 2 has better hardware 32-bit emulator plus better overall Itanium architecture, so 32-bit performance increases to around equal to 300MHz Pentium II(1GHz Itanium 2 has twice the performance or better compared to 800MHz Itanium in native code). That's pretty bad, makes running 32-bit practically useless, and according to the review, the compatibility was not so good either, as Quake 3 wouldn't install(not that running Quake 3 on Pentium 100MHz equivalent isn't sort of a push). Plus it takes additional die space and power consumption, which is not that much but a lot for a almost useless feature.

    So Intel introduced a dynamic software translator for the Itanium called IA-32EL(Execution Layer). By translating x86 instructions to EPIC instructions and optimizing them on run-time, performance improved dramatically while, taking out the need to have hardware emulator. 1.5GHz Itanium 2 with 6MB L3 cache is now equal to equivalently clocked Xeon MP(with hardware it would have been equal to 450MHz Pentium II) or better, which isn't that bad, and much better than the hardware one.

    Montecito seems to not have the hardware emulator anymore.
    Reply
  • JarredWalton - Tuesday, August 23, 2005 - link

    Dang, I *swear* I read an article on HP.com or Intel.com stating Itanium 2 was 8-wide. I can't find it anymore, but there are many saying 6-wide. Weird. Anyway, I've read plenty about the rest of the Itanium architecture, and I don't know why you're suddenly going off about it. I'll correct the issue width statement, though.

    Not like it matters now, as we all know Conroe is 4-wide now. (I really expected that to be the case, but was told to make it less certain and more speculative for the article.)
    Reply
  • IntelUser2000 - Thursday, August 25, 2005 - link

    http://www.intel.com/design/itanium2/datashts/2509...">http://www.intel.com/design/itanium2/datashts/2509...

    The intro shows that its 6-wide, 8-stage pipeline deep architecture. 8 does stand for something but I forgot what. I babbled on because it wasn't directed all at you, but I hoped somebody who didn't know and want to know may look at it.
    Reply
  • JarredWalton - Friday, August 26, 2005 - link

    Argh! WTF is going on? Am I senile? I'm positive I read something about Itanium 2 (McKinley, etc.) being more than 8 pipeline stages. It stated something about the 8 stages of Merced being part of the reason Itanium 1 never reached higher clock speeds. Damn... people must just make stuff up about these architectures. :| Reply
  • IntelUser2000 - Thursday, September 1, 2005 - link

    quote:

    Argh! WTF is going on? Am I senile? I'm positive I read something about Itanium 2 (McKinley, etc.) being more than 8 pipeline stages. It stated something about the 8 stages of Merced being part of the reason Itanium 1 never reached higher clock speeds. Damn... people must just make stuff up about these architectures. :|


    Itanium "Merced" is 10 stage pipelines. Nearly everyone that looked at the architecture said it was a bloated design, that was released in haste. By improving design tremendously over Itanium, Itanium 2 Mckinley reduces that to 8 stage pipeline while clocking 25% higher at the SAME process.

    Itanium-800MHz, 0.18 micron, 10 stage pipeline, 9 stage branch miss stages
    Itanium 2-1GHz, 0.18 micron, 8 stage pipeline, 7 stage branch miss stages
    Reply
  • nserra - Friday, August 19, 2005 - link

    I agree IntelUser2000, but even so, if each core used c&q with some disable core capability, would be in the 30W per core range (120W total) right on track with prescott 2M and Pentium D.

    I don’t know if you noticed, but amd added more power to their designs while their processor are consuming less.... that must be because:

    Good reasons first:
    -amd will achieve higher clock speeds 3.4 GHz and up
    -amd is already thinking in 4 cores processors

    Bad reasons:
    -amd will come with some bad 65nm tech
    -or will come with some bad core (M2 with rev.F prescott like)
    Reply
  • dwalton - Monday, August 15, 2005 - link


    "Intel Q3'05 Roadmap: Conroe Appears, Speculation Ensues"

    I almost spit my coffee onto the keyboard when i read that title. Came off to me as Intel released a roadmap showing the Conroe release in the third quarter of this year.
    Reply
  • JarredWalton - Monday, August 15, 2005 - link

    Sorry to disappoint. :p

    Intel's lead time on the roadmap is about 18 months, though the initial details are often lacking. With Conroe/Merom being a new architecture, I doubt Intel will do so much as mention a clock speed without NDAs.
    Reply
  • IntelUser2000 - Friday, August 12, 2005 - link

    Intel's 45nm is supposed to signal high-K, metal gates, and possibly tri-gate transistor structure. By using tri-gate, its supposed to be fully depleted substrate from the start. So, if they implement what they say they will according to their presentations:

    -High-K
    -Metal
    -Tri-gate, which brings FD-SOI

    We should see Yonah before worrying about Conroe. The specs of Yonah is pretty interesting.
    Reply
  • JarredWalton - Saturday, August 13, 2005 - link

    Yonah looks interesting in some ways, but as far as I can tell it's just Dothan on 65nm with dual cores, improved uops-fusion, and hopefully better FP/SIMD support. I haven't even heard anything to indicate it will have 64-bit extensions, which makes it less than Conroe in my book. Not that 64-bit is the be-all, end-all, but I'm pretty sure I've bought my last 32-bit CPU now. I'd hate to get stuck upgrading for Longhorn just because I didn't bother with a 64-bit enabled processor. Bleh... Longhorn and 64-bit is really just hype anyway, but we'll be forced that way like it or not. Hehehe. Reply

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