Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed
by Dr. Ian Cutress & Andrei Frumusanu on August 19, 2021 9:00 AM ESTInstruction Sets: Alder Lake Dumps AVX-512 in a BIG Way
One of the big questions we should address here is how the P-cores and E-cores have been adapted to work inside a hybrid design. One of the critical aspects in a hybrid design is if both cores support different levels of instructions. It is possible to build a processor with an unbalanced instruction support, however that requires hardware to trap unsupported instructions and do core migration mid-execution. The simple way to get around this is to ensure that both types of cores have the same level of instruction support. This is what Intel has done in Alder Lake.
In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled.
Intel’s journey with AVX-512 has been long and fragmented. Some workloads can be vectorised – multiple bits of consecutive data all require the same operation, so you can pack them into a single register and perform it all at once with a single instruction. Designed as its third generation of vector instructions (AVX is 128-bit, AVX2 is 256-bit, AVX512 is 512-bit), AVX-512 was initially found on server processors, then mobile, and we found it in the previous version of desktop processors. At the time, Intel stated that by enabling AVX-512 on its processor line from top to bottom, it would encourage greater adoption, and they were leaning hard into this missive.
But that all changes with Alder Lake. Both desktop processors and mobile processors will now have AVX-512 disabled in all scenarios. But the silicon will still be physically present in the core, only because Intel uses the same core in its next generation server processors called Sapphire Rapids. One could argue that if the AVX-512 unit was removed from the desktop cores that they would be a lot smaller, however Intel has disagreed on this point in previous launches. What it means is that for the consumer parts we have some extra dark silicon in the design, which ultimately might help thermals, or absorb defects.
But it does mean that AVX-512 is probably dead for consumers.
Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512.
On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2. In testing with the previous generation Tremont Atom core, at 2.9 GHz it performed similarly to a Haswell 2.9 GHz Celeron processor, i.e. identical in non-AVX2 situations. By adding AVX2, plus fundamental performance increases, we’re told to expect ‘Skylake-like performance’ from the new E-cores. Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support.
By enabling AVX2 on the E-cores, Intel is also integrating support for VNNI instructions for neural network calculations. In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake. So while AVX-512 might be dead here, at least some of those AI acceleration features are carrying over, albeit in AVX2 form.
For the data center versions of these big cores, Intel does have AVX-512 support and new features for matrix extensions, which we will cover in that section.
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mode_13h - Friday, August 20, 2021 - link
With a launch date in just a few months, their reference documentation should already be updated with info about the supported instructions on Golden Cove.I'd be interested in hearing why these features are of interest to you.
mode_13h - Thursday, August 19, 2021 - link
> look for Cinebench R20 scores for one Gracemont thread around 478 then> (Skylake 6700K scored 443).
No, because the 8% greater perf is on spec int, and Cinebench is not an integer workload!
> If that’s the case, where is our 64-core Atom version for HEDT?
That market will probably be better-served by a Sapphire Rapids-derived chip with with much more floating-point horsepower per core.
However, a 128-core Gracemont-based server CPU could perhaps be interesting for mostly integer workloads.
> along with a 5000-entry branch target cache
Is that not the same as a BTB?
> So it’s a bit insane to have 17 execution ports here
But they're more special-purpose, right? If you make each less versatile, the natural consequence is that you need more of them.
> in the E-core there are two separate schedulers
A little like Bulldozer, no? Except they're both being fed by just one thread.
> if each core is fully loaded, there is only 512 KB of L2 cache per core before
> making the jump to main memory
Unless I'm missing something, 4 MB / 4 cores = 1 MB / core
GeoffreyA - Friday, August 20, 2021 - link
"in the E-core there are two separate schedulers"I think that's related to the ports being divided into integer and vector sides. Possibly, one scheduler is handling the integer work, and one the FP. It's interesting that this design is following in the tracks of Zen (and even the Athlon). Also, it's ROB is 256 entries, which is same as Zen 3's. Intel is slowly working Atom up to be their main design.
mode_13h - Saturday, August 21, 2021 - link
> Intel is slowly working Atom up to be their main design.I don't know about being their main design, but perhaps they're worried their P-cores are too uncompetitive in perf/W with ARM server cores. So, I could imagine them making a bigger push for server CPUs built around E-cores.
dullard - Thursday, August 19, 2021 - link
"For users looking for more information about Thread Director on a technical, I suggest reading this document and going to page 185, reading about EHFI – Enhanced Hardware Frequency Interface."Ian, can you please link that document? Thanks.
TeXWiller - Thursday, August 19, 2021 - link
I had a strong impression that Windows 11 will be "published" well (months) before Alder Lake based products come to market.drothgery - Friday, August 20, 2021 - link
Intel has an event scheduled at the end of October that seems to be strongly rumored as the official launch event for Adler Lake. That's only two months from now. How it actually performs is TBD, but I'd bet a lot on working systems in reviewers' hands before November.Dr_b_ - Thursday, August 19, 2021 - link
looking really good, sad to lose AVX512 thoughconcerns:
-no real substantive availability on release date
-high prices for motherboards/RAM/CPU and scalping, we are still in a pandemic with global supply chain disruptions
-buggy motherboard/OS
-no Linux support
mode_13h - Friday, August 20, 2021 - link
They didn't say "no Linux support". Rather, they said the thread director wouldn't initially have explicit Linux support. I'm sure there will be workarounds, probably along the lines of how Windows 10 sees the Big.Little cores. Remember that Linux has scheduled workloads on Big.Little configurations in Android, for at least a decade.flensr - Thursday, August 19, 2021 - link
That on-chip embedded microprocessor that tracks threading... It gets to talk to the OS. How cool is that as a target for hackers?