Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510
by Andrei Frumusanu on May 25, 2021 9:00 AM EST- Posted in
- SoCs
- CPUs
- Arm
- Smartphones
- Mobile
- Cortex
- ARMv9
- Cortex-X2
- Cortex-A710
- Cortex-A510
The Cortex-A710: More Performance with More Efficiency
While the Cortex-X2 goes for all-out performance while paying the power and area penalties, Arm's Cortex-A710 design goes for a more efficient approach.
First of all, the new product nomenclature now is self-evident in regards to what Arm will be doing going forward- they’re skipping the A79 designation and simply starting fresh with a new three-digit scheme with the A710. Not very important in the grand scheme of things but an interesting marketing tidbit.
The Cortex-A710, much like the X2, is an Armv9 core with all new features that come with the new architecture version. Unlike the X2, the A710 also supports EL0 AArch32 execution, and as mentioned in the intro, this was mostly a design choice demanded by customers in the Chinese market where the ecosystem is still slightly lagging behind in moving all applications over to AArch64.
In terms of front-end enhancements, we’re seeing the same branch prediction improvements as on the X2, with larger structures as well as better accuracy. Other structures such as the L1I TLB have also seen an increase from 32 entries to 48 entries. Other front-end structures such as the macro-OP cache remain the same at 1.5K entries (The X2 also remains at 3K entries).
A very interesting choice for the A710 mid-core is that Arm has reduced the macro-OP cache and dispatch stage throughputs from 6-wide to 5-wide. This was mainly a targeted power and efficiency optimization for this generation, as we’re seeing a more important divergence between the Cortex-A and Cortex-X cores in terms of their specializations and targeted use-cases for performance and power.
The dispatch stage also features the same optimizations as on the X2, removing 1 cycle from the pipeline towards an overall 10-cycle pipeline design.
Arm also focuses on core improvements that affect the uncore parts of the system, which take place thanks to the new improvements in the prefetcher designs and how they interact with the new DSU-110 (which we’ll cover later). The new combination of core and DSU are able to reduce access from the core towards the L3 cache, as well as reducing the costly DRAM accesses thanks to the more efficiency prefetchers and larger L3 cache.
In terms of IPC, Arm advertises +10%, but again the issue with this figure here is that we’re comparing an 8MB L3 cache design to a 4MB L3 cache design. While this is a likely comparison for flagship SoCs next year, because the Cortex-A710 is also a core that would be used in mid-range or lower-end SoCs which might use much smaller L3 caches, it’s unlikely we’ll be seeing such IPC improvements in that sector unless the actual SoCs really do also improve their DSU sizes.
More important than the +10% improvement in performance is that, when backing off slightly in frequency, we can see that the power reduction can be rather large. According to Arm, at iso-performance the A710 consumes up to 30% less power than the Cortex-A78. This is something that would greatly help with sustained performance and power efficiency of more modestly clocked “middle” core implementations of the Cortex-A710.
In general, both the X2 and the A710’s performance and power figures are quite modest, making them the smallest generation-over-generation figures we’ve seen from Arm in quite a few years. Arm explains that due to this generation having made larger architectural changes with the move to Armv9, there has been an impact in regards to the usual efficiency and performance improvements that we’ve seen in prior generations.
Both the X2 and the A710 are also the fourth generation of this Austin microarchitecture family, so we’re hitting a wall of diminishing returns and maturity of the design. A few years ago we were under impression that the Austin family would only go on for three generations before handing things over to a new clean-sheet design from the Sophia team, but that original roadmap has been changed, and now we'll be seeing the new Sophia core with larger leaps in performance being disclosed next year.
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Silver5urfer - Tuesday, May 25, 2021 - link
Forgot that 32bit only thing. Apple does it everyone follows lol, on Phones the apps may be very limited for 32bit I do not know how many but some useful software might still be not updated but it might work, there is an app called DiskUsage that makes the WinDirStat type look and it's blazing fast plus works with root too. unfortunately that might be not working in the latest garbage Android 12 since it won't have storage access with SAF and Scoped disaster. There could be others..Thankfully it's not Windows which has a ton of applications on 32Bit. So pretty much some of the phones are getting outdated with this 64Bit only bs change, but since it's anyways planned obsolescence it won't matter by the time 64Bit only CPUs come like this phones which support 32bit would be dead, barring those amazing phones which have custom rom with removable batteries, they should be used for nice souvenirs if there's a DAC then like a DAP.
GeoffreyA - Thursday, May 27, 2021 - link
"Apple does it everyone follows"Popular opinion (more so when led by Apple) is like a wildfire, sweeping everything in its path.
mode_13h - Wednesday, May 26, 2021 - link
Blame consumers. Serviceable devices are more bulky and add some cost. In particular, the modular phone concept has been pursued a couple times, but never got traction.I don't like disposable hardware, but that's a sad reality of phones, tablets, and ultra-portables. I wanted to do the next best thing and use a phone with open software, but MeeGo and Firefox Phone both failed and none of the current Linux-based phone projects seem to be gaining much traction.
FWIW, my current phone does have a replaceable battery, which I had to do after the original one started swelling. It's not *easily* replaceable, but you can still do it or pay someone a little money to do it for you.
melgross - Thursday, May 27, 2021 - link
Serviceable mobile devices are also less reliable, and have smaller batteries.del42sa - Wednesday, May 26, 2021 - link
Bulldozer strikes back . LoLPS: it´s interesting design though
GeoffreyA - Thursday, May 27, 2021 - link
Shows that AMD wasn't completely bonkers.del42sa - Thursday, May 27, 2021 - link
it wasn´t a bad idea or bad arch. it was just very bad implementedusiname - Wednesday, May 26, 2021 - link
a510 vs a73 - 25% slower with 35% better power efficiency, 4 years of inovations for you.ET - Wednesday, May 26, 2021 - link
I think it's clear from the DVFS slide on the A510 page of the article that the main difference between the A55 and A510 is that the A510 can reach much higher performance with much higher power use.So yes, anyone expecting much better efficiency will be disappointed.
A510 does lead the way to pure "small core" designs that reach reasonable performance on one hand and low power on the other hand.
Still, I haven't seen a figure comparing core size, and that would be a very important measure.
mode_13h - Thursday, May 27, 2021 - link
> anyone expecting much better efficiency will be disappointed.Efficiency can come from a smaller process node. The A55 and A510 were compared at ISO-process.