SPEC - Single-Threaded Performance

Single-thread performance of server CPUs usually isn’t the most important metric for most scale-out workloads, but there are use-cases such as EDA tools which are pretty much single-thread performance bound.

Power envelopes here usually don’t matter, and what is actually the performance factor that comes at play here is simply the boost clocks of the CPUs as well as the IPC improvement, and memory latency of the cores. 

The one hiccup for the Xeon 8380 this generation is the fact that although there’s plenty of IPC gains to be had compared to previous microarchitectures, the new SKU is only boosting up to 3.4GHz, whereas the 8280 was able to boost up to 4GHz, which is a 15% deficit.

SPECint2017 Rate-1 Estimated Scores

Even with the clock frequency disadvantage, thanks to the IPC gains, much improved memory bandwidth, as well as the much larger L3 cache, the new Ice Lake part to most of the time beat the Cascade Lake part, with only a couple of compute-bound core workloads where it falls behind.

SPECfp2017 Rate-1 Estimated Scores

The floating-point figures are more favourable to the ICX architecture due to the stronger memory performance.

SPEC2017 Rate-1 Estimated Total

Overall, the new Xeon 8380 at least manages to post slight single-threaded performance increases this generation, with larger gains in memory-bound workloads. The 8380 is essentially on par with AMD’s 7763, and loses out to the higher frequency optimised parts.

Intel has a few SKUs which offers slightly higher ST boost clocks of up to 3.7GHz – 300Mhz / 8.8% higher than the 8380, however that part is only 8-core and features only 18MB of cache. Other SKUS offer 3.5-3.6GHz boosts, but again less cache. So while the ST figures here could improve a bit on those parts, it’s unlikely to be significant.

SPEC - Multi-Threaded Performance SPEC - Per-Core Performance under Load
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  • Oxford Guy - Sunday, April 11, 2021 - link

    'The faulty logic I see is that you seem to believe it's the review's job to...'

    'I think it could be appropriate to do that sort of thing, in articles that...'

    Don't contradict yourself or anything.

    If you're not interested in knowing how fast a CPU is that's ... well... I don't know.

    Telling people to go for marketing info (which is inherently deceptive — the entire fundamental reason for marketing departments to exist) is obviously silly.
  • mode_13h - Monday, April 12, 2021 - link

    > Don't contradict yourself or anything.

    I think the point of confusion is that I'm drawing a distinction between the initial product review and subsequent follow-up articles they often publish to examine specific points of interest. This would also allow for more time to do a more thorough investigation, since the initial reviews tend to be conducted under strict deadlines.

    > If you're not interested in knowing how fast a CPU is that's ... well... I don't know.

    There's often a distinction between the performance, as users are most likely to experience it, and the full capabilities of the product. I actually want to know both, but I think the former should be the (initial) priority.
  • ballsystemlord - Thursday, April 8, 2021 - link

    Spelling and grammar errors (there are a lot!):

    "At the same time, we have also spent time a dual Xeon Gold 6330 system from Supermicro, which has two 28-core processors,..."
    Nonsensical English: "time a duel". I haven't the faintest what you were trying to say.

    "DRAM latencies here are reduced by 1.7ns, which isn't very much a significant difference,..."
    Either use "very much", or use "a significant":
    DRAM latencies here are reduced by 1.7ns, which isn't a very significant difference,..."

    "Inspecting Intel's prior disclosures about Ice Lake SP in last year's HotChips presentations, one point sticks out, and that's is the "SpecI2M optimisation" where the system is able to convert traditional RFO (Read for ownership) memory operations into another mechanism"
    Excess "is":
    "Inspecting Intel's prior disclosures about Ice Lake SP in last year's HotChips presentations, one point sticks out, and that's the "SpecI2M optimisation" where the system is able to convert traditional RFO (Read for ownership) memory operations into another mechanism"

    "It's a bit unfortunate that system vendors have ended up publishing STREAM results with hyper optimised binaries that are compiled with non-temporal instructions from the get-go, as for example we would not have seen this new mechanism on Ice Lake SP with them"
    You need to rewrite the sentance or add more commas to break it up:
    "It's a bit unfortunate that system vendors have ended up publishing STREAM results with hyper optimised binaries that are compiled with non-temporal instructions from the get-go, as, for example, we would not have seen this new mechanism on Ice Lake SP with them"

    "The latter STREAM results were really great to see as I view is a true design innovation that will benefit a lot of workloads."
    Exchange "is" for "this as":
    "The latter STREAM results were really great to see as I view this as a true design innovation that will benefit a lot of workloads."
    Or discard "view" and rewrite as a diffinitive instead of as an opinion:
    "The latter STREAM results were really great to see as this is a true design innovation that will benefit a lot of workloads."

    "Intel's new Ice Lake SP system, similarly to the predecessor Cascade Lake SP system, appear to be very efficient at full system idle,..."
    Missing "s":
    "Intel's new Ice Lake SP system, similarly to the predecessor Cascade Lake SP system, appears to be very efficient at full system idle,..."

    "...the new Ice Lake part to most of the time beat the Cascade Lake part,..."
    "to" doesn't belong. Rewrite:
    "...the new Ice Lake part can beat the Cascade Lake part most of the time,..."

    "...both showcasing figures that are still 25 and 15% ahead of the Xeon 8380."
    Missing "%":
    "...both showcasing figures that are still 25% and 15% ahead of the Xeon 8380."

    "Intel had been pushing very hard the software optimisation side of things,..."
    Poor sentance structure:
    "Intel had been pushing the software optimisation side very hard,..."

    "...which unfortunately didn't have enough time to cover for this piece."
    Missing "we":
    "...which unfortunately we didn't have enough time to cover for this piece."

    "While we are exalted to finally see Ice lake SP reach the market,..."
    "excited" not "exalted":
    "While we are excited to finally see Ice lake SP reach the market,..."

    Thanks for the article!
  • Oxford Guy - Sunday, April 11, 2021 - link

    Perhaps Purch would be willing to take you on as a volunteer unpaid intern for proofreading for spelling and grammar?

    I would think there are people out there who would do it for resume building. So... if it bothers you perhaps you should make an inquiry.
  • evilpaul666 - Saturday, April 10, 2021 - link

    Are the W-1300s going to use 10nm this year?
  • mode_13h - Saturday, April 10, 2021 - link

    You mean the bottom-tier Xeons? Those are just mainstream desktop chips with less features disabled, so that question depends on when Alder Lake hits.

    I'd say "no", because the Xeon versions typically lag the corresponding mainstream chips by a few months. So, if Alder Lake launches in November, then maybe we get the Xeons in February-March of next year.

    The more immediate question is whether they'll release a Xeon version of Rocket Lake. I think that's likely, since they skipped Comet Lake and there are significant platform enhancements for Rocket Lake.
  • AdrianBc - Monday, April 12, 2021 - link

    No, the W-1300 Xeons will be Rocket Lake. The top model will be Xeon W-1390P, which will be equivalent to the top i9 Rocket Lake, with 125 W TDP and 5.3 GHz maximum turbo.
  • rahvin - Tuesday, April 20, 2021 - link

    Andre does some of the best server reviews available, IMO.
  • KKK11 - Tuesday, May 11, 2021 - link

    That is a curious-looking wafer. I thought it was fake at first but then I noticed the alignment notch. Actually, I'm still not convinced it's real because I have seen lots and lots of wafers in various stages of production and I have never seen one where partial chips go all the way out to the edges. It's a waste of time to deal with those in the steppers so no one does that.

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