Cache and TLB Updates

One of the biggest changes in the new Sunny Cove core is the cache hierarchy. Throughout most of the last decade, Intel has kept the same cache configuration among its server cores with very few changes, aside from improving the micro-op cache through Sandy Bridge today, but with Sunny Cove, we get some key updates.

From our microarchitecture disclosure article, we know that Sunny Cove brings with it an increased L1 data cache, as well as a doubled L2 cache, from Skylake. With this comes more associativity as well.

Core Cache Comparison
Sunny
Cove
AnandTech Cannon
Lake
Skylake Sandy
Bridge
  AMD
Zen 2
48 KB
12-way
L1-D 32 KB
8-way
32 KB
8-way
32 KB
8-way
  32 KB
8-way
32 KB
8-way
L1-I 32 KB
8-way
32 KB
8-way
32 KB
8-way
  32 KB
8-way
512 KB
8-way
L2 256 KB
4-way
256 KB
4-way
256 KB
8-way
  512 KB
8-way
2 MB
16-way
L3/core 2 MB
16-way
2 MB
16-way
2MB
16-way
  4 MB
16-way
2304 uOp Cache 1536 1536 1536   4096

I’ve also included the size of the micro-op cache in this comparison, because we understand that the L1-I and the micro-op cache are typically located next to each other in the die design – increasing the size of one typically means limiting the size of the other, however given that both of them work to accelerate the same types of data, it is important to find the right balance: AMD for Zen 2 decided to halve the L1-I and double its associativity, and then double the micro-op cache from 2k to 4k entries. For Sunny Cove, Intel has increased the L1-D by 50%, but also increased the micro-op cache by 50%, taking advantage of the second generation 10nm process.

In the above latency graph comparison, we can notably see the new increased cache capacities. The L1’s increase from 32KB to 48KB is well visible, as well as the L2 increase from 256KB to 512KB.

On the part of the L2 it’s interesting to see that again the new core’s TLB structures don’t quite cover the whole capacity of the L2 and that’s why the latter half of the L2 has worse access latencies for L1D TLB miss patterns.

L3 latencies look similar, however we’ll dwell into that just in a bit. The DRAM latencies of course are apples and oranges in this case as Intel’s new LPPDR4X memory controller in the new ICL part doesn’t have a counter-part we can compare to, but as expected the memory latency is notably worse than a desktop part so no big surprises there.

What’s rather disappointing however is that we’re not really seeing any kind of change to the prefetchers and our access patterns between the two microarchitectures look identical. We had expected Intel to improve in this regard, but alas it seems, at least for our test cases, there’s been no improvements.

One of the major balancing acts with cache sizes is also cache latency. The bigger the cache, the longer it takes to retrieve data from it – increasing associativity can do this as well. Intel for the longest time has cited a 4-cycle latency to its L1 cache, and a 12-cycle latency to its L2 cache. This changes, in quite a substantial way.

Core Cache Latency (in cycles)
Sunny Cove AnandTech Cannon
Lake
Skylake Sandy
Bridge
  AMD
Zen 2
5 L1 4 4 4   4
13 L2 12 ~12 12   12
30-36 L3   26-37     34

Due to the increase in the L1 cache, that 4-cycle latency is now a 5-cycle latency. Intel is hoping that its double L1 store bandwidth will help hide that latency, however adding 20% latency onto every data fetch is a heavy hit to take. This is why a lot of the rest of the core is also beefed up, so work can still continue to cover for this extra cycle. It is worth noting that Intel’s Atom cores in the past had an L1 latency of 3 cycles, however they have also since moved to 4-cycle.

The L2 also changes, from 12 cycles to 13 cycles. You can’t double a cache for free, and it is interesting to note here that now AMD and Intel share the same L2 cache size and the same associativity, however AMD has a cycle advantage on Intel. This has a knock on effect for L3 cache latency too, which has increased from ~26-37 cycles to ~30-36 cycles on Intel, from Skylake. The latency here isn’t uniform because the cache isn’t uniform, and accessing non-local L3 slices comes with a latency penalty, as say opposed to AMD’s uniform latency L3.

One of the biggest additions Intel was keen to make in our Sunny Cove microarchitecture disclosure is the increase in the L1 bandwidth. Based on our testing, Skylake’s L1 data cache was capable of 2x32-byte read and 1x32-byte write per clock. For Sunny Cove this has increased, but it gets a bit more complicated. In one clock Sunny cove can perform 2x64-byte reads and either 1x64-byte write, or 1x32-byte write, or 2x16-byte writes. So both reads and writes, at peak, have doubled with bit width, with the write configurations being a bit more complex.

We can see the direct effects of the bandwidth change in our bandwidth tests. The L1 store bandwidth is extremely evident as it measures in at 222GB/s on the ICL part, while only reaching 139GB/s on the 28% higher clocked 9900K. If we normalise for frequency, we indeed see a doubling of the store bandwidth of the new core.

The L2 cache bandwidth looks unchanged from Skylake – the part here lags behind with an equal amount to the frequency difference. Surprisingly, the L3 bandwidth fares quite well here and is almost at parity to the desktop 9900K even though the frequency difference. The DRAM bandwidth is inferior on the ICL mobile chip, but again that’s to be expected due to the apples and oranges DRAM architecture comparison.

Moving on to the TLB configurations, and it turns out that Intel has moved where this data is stored. This data is typically stored in CPUID.02h, however it is now found in CPUID.18h, and the info between different page sizes and capabilities is now given as subdivisions. The TLBs look as follows, and broken down into configurations:

Sunny Cove TLB
AnandTech Type Entries Associativity
L1-D 4K 64 4-way
L1-D 2M 32 4-way
L1-D 1G 8 full
L1-I 4K+2M 8 full
L1-I 4K+2M+1G 16 full
L2 4K+2M 1024 8-way
L2 4K+1G 1024 8-way

This means that for 4K and 2M L1-I entries, there are a total 8+16 = 24 possible, but only 16 1G possible. For 4K L2 entries, there are 1024 + 1024 = 2048 entries possible, however only 1024 each of 2M/1G are possible. The peak numbers align with what Intel has told us in our microarchitecture disclosure, however it is good to dive into what is possible.

Intel 10nm Ice Lake, Sunny Cove, and Gen11 Tested: Details Inside Security Updates, Improved Instruction Performance and AVX-512 Updates
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  • 0ldman79 - Friday, August 2, 2019 - link

    Uh...

    They reworked the entire 10nm process to get it going.

    This isn't impossible, it is expensive and time consuming.

    They've spent the $$$ and at least a year working on it.

    It is hardly unheard of that the single most successful tech company on the planet figured out a problem.
    Reply
  • yeeeeman - Wednesday, June 17, 2020 - link

    This is not a reasonable argument that he gave you. He just wanted, like a lot of people today, to show his hate for Intel. He's not seeing things straight anymore and I really don't understand this hate speech that many people have today about certain products. It is what it is, reviewers test them and there is not much else to say. I guess the reason is more people are being stupid these days. Reply
  • dguy6789 - Thursday, August 1, 2019 - link

    Stop whining. The article is well written and provides plenty of information on Intel's new chip. Nobody gives a hoot about your tinfoil hat nonsense. Reply
  • close - Tuesday, August 6, 2019 - link

    @dguy6789, obviously plenty of people do. AT did somehow manage to bungle repeatedly, always in positive ways for Intel, not so positive for the competition.

    And as these things go, if it turns out AT's current article is spot on then not much will change (past mistakes were still made). But if it turns out they were played *again* (assuming ignorance not bad intentions) and AT offers the same anemic retraction then it's going to be pretty clear where the editorial team stands.
    Reply
  • AshlayW - Thursday, August 1, 2019 - link

    You can't please everyone lol. I thought the article was great, informative and, imo, fair. Interesting to get a first look at the architecture and I enjoy reading your assessments on the results, puts it into context for me. :)

    I'm a pretty hardcore Ryzen fan too :P
    Reply
  • MDD1963 - Friday, August 2, 2019 - link

    Yes, how *dare* anyone publish *anything* that could be read as positive about new recent Intel products' performance gains, and the sheer audacity to do so within less than a month of the Ryzen 3000 launch! :/ Reply
  • jospoortvliet - Friday, August 2, 2019 - link

    It might be an obvious marketing ploy (I agree with that assessment) and that can be pointed out but a journalist wouldn’t be doing their job any better by ignoring this opportunity... both amd and intel as well as NVIDIA play these games all the time. Reply
  • brakdoo - Thursday, August 1, 2019 - link

    Yeah Intel is trying to give journalists more info than the public for the past few months/quarters so that these people think they are special because they are "insiders" (they don't have much else to be proud of).

    These journalists talked so much about IPC over these months but it turned out to be just BS because IPC is nothing without frequency (to a certain extent AMD did the same stupid IPC thing). It is obvious that the frequency issue is not just about 10 nm but instead it's caused by this messed up architecture. Otherwise Intel would just sell 14 nm Ice lake CPUs...

    They even fooled these tech sites with the graphics performance. It's barely faster than Iris plus 655.

    AMD had a bad history of weird journalist events and giving too much NDA info but Intel turned it into a real shitshow.
    Reply
  • Gondalf - Thursday, August 1, 2019 - link

    Likely you have some problems with Sunny Cove that is clearly superior than Zen 2 even without fast desktop DRAM and without an insane amount of L3.
    Pretty certain you are trying to realize how fast will be Ice Lake EP in server space.
    The end of a dream??? Yes it is.

    Obviously Intel is preparing itself to finer nodes that will not allow fast clock speeds anymore but an intersting density instead.

    This review is a nice example of what will be the future Intel core performance cadence in the next two years.
    Many thanks Haifa Team.

    About GPU, it is pretty good because now it performs at 15W level and without an expensive eDRAM. Try to run the new GPU within 28W and you will have an idea of the advantages of the new ark vs. 9.5.
    Reply
  • 0ldman79 - Friday, August 2, 2019 - link

    Brakdoo is way off in his assertions, but I believe you have rose colored glasses too.

    Intel got the efficient process working, not the high performance one. They still have 14nm planned out for another year at least.

    It isn't just the lithography that is the problem either, Sunny Cove is a different architecture, it just might not clock as high. We'll have to wait and see how that all works out.

    I do agree though, speeds are probably going to stall if not regress moving forward. It's just a lot of amps going through a tiny circuit. 14nm might have been the sweet spot to get the highest clock speeds. Smaller circuits will only get hotter carrying the same current. Unless they significantly lower power usage it is going to be a problem.

    Apparently .7v is the switching point for silicon semi-conductors, below that the transistors don't switch, so to go beyond 7nm or 5nm they're very likely going to have to move to a more conductive material to lower the switching point as well as resistance (heat buildup).

    Interesting times...
    Reply

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