The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700
by Ian Cutress on March 2, 2017 9:00 AM ESTThoughts and Comparisons
Throughout AMD's road to releasing details on Zen, we have had a chance to examine the information on the microarchitecture often earlier than we had expected to each point in the Zen design/launch cycle. Part of this is due to the fact that internally, AMD is very proud of their design, but some extra details (such as the extent of XFR, or the size of the micro-op cache), AMD has held close to its chest until the actual launch. With the data we have at hand, we can fill out a lot of information for a direct comparison chart to AMD’s last product and Intel’s current offerings.
| CPU uArch Comparison | ||||
| AMD | Intel | |||
| Zen 8C/16T 2017 |
Bulldozer 4M / 8T 2010 |
Skylake Kaby Lake 4C / 8T 2015/7 |
Broadwell 8C / 16T 2014 |
|
| L1-I Size | 64KB/core | 64KB/module | 32KB/core | 32KB/core |
| L1-I Assoc | 4-way | 2-way | 8-way | 8-way |
| L1-D Size | 32KB/core | 16KB/thread | 32KB/core | 32KB/core |
| L1-D Assoc | 8-way | 4-way | 8-way | 8-way |
| L2 Size | 512KB/core | 1MB/thread | 256KB/core | 256KB/core |
| L2 Assoc | 8-way | 16-way | 4-way | 8-way |
| L3 Size | 2MB/core | 1MB/thread | >2MB/cire | 1.5-3MB/core |
| L3 Assoc | 16-way | 64-way | 16-way | 16/20-way |
| L3 Type | Victim | Victim | Write-back | Write-back |
| L0 ITLB Entry | 8 | - | - | - |
| L0 ITLB Assoc | ? | - | - | - |
| L1 ITLB Entry | 64 | 72 | 128 | 128 |
| L1 ITLB Assoc | ? | Full | 8-way | 4-way |
| L2 ITLB Entry | 512 | 512 | 1536 | 1536 |
| L2 ITLB Assoc | ? | 4-way | 12-way | 4-way |
| L1 DTLB Entry | 64 | 32 | 64 | 64 |
| L1 DTLB Assoc | ? | Full | 4-way | 4-way |
| L2 DTLB Entry | 1536 | 1024 | - | - |
| L2 DTLB Assoc | ? | 8-way | - | - |
| Decode | 4 uops/cycle | 4 Mops/cycle | 5 uops/cycle | 4 uops/cycle |
| uOp Cache Size | 2048 | - | 1536 | 1536 |
| uOp Cache Assoc | ? | - | 8-way | 8-way |
| uOp Queue Size | ? | - | 128 | 64 |
| Dispatch / cycle | 6 uops/cycle | 4 Mops/cycle | 6 uops/cycle | 4 uops/cycle |
| INT Registers | 168 | 160 | 180 | 168 |
| FP Registers | 160 | 96 | 168 | 168 |
| Retire Queue | 192 | 128 | 224 | 192 |
| Retire Rate | 8/cycle | 4/cycle | 8/cycle | 4/cycle |
| Load Queue | 72 | 40 | 72 | 72 |
| Store Queue | 44 | 24 | 56 | 42 |
| ALU | 4 | 2 | 4 | 4 |
| AGU | 2 | 2 | 2+2 | 2+2 |
| FMAC | 2x128-bit | 2x128-bit 2x MMX 128-bit |
2x256-bit | 2x256-bit |
Bulldozer uses AMD-coined macro-ops, or Mops, which are internal fixed length instructions and can account for 3 smaller ops. These AMD Mops are different to Intel's 'macro-ops', which are variable length and different to Intel's 'micro-ops', which are simpler and fixed-length.
Excavator has a number of improvements over Bulldozer, such as a larger L1-D cache and a 768-entry L1 BTB size, however we were never given a full run-down of the core in a similar fashion and no high-end desktop version of Excavator will be made.
This isn’t an exhaustive list of all features (thanks to CPU World, Real World Tech and WikiChip for filling in some blanks) by any means, and doesn’t paint the whole story. For example, on the power side of the equation, AMD is stating that it has the ability to clock gate parts of the core and CCX that are not required to save power, and the L3 runs on its own clock domain shared across the cores. Or the latency to run certain operations, which is critical for workflow if a MUL operation takes 3, 4 or 5 cycles to complete. We have been told that the FPU load is two cycles quicker, which is something. The latency in the caches is also going to feature heavily in performance, and all we are told at this point is that L2 and L3 are lower latency than previous designs.
A number of these features we’ve already seen on Intel x86 CPUs, such as move elimination to reduce power, or the micro-op cache. The micro-op cache is a piece of the puzzle we wanted to know more about from day one, especially the rate at which we get cache hits for a given workload. Also, the use of new instructions will adjust a number of workloads that rely on them. Some users will lament the lack of true single-instruction AVX-2 support, however I suspect AMD would argue that the die area cost might be excessive at this time. That’s not to say AMD won’t support it in the future – we were told quite clearly that there were a number of features originally listed internally for Zen which didn’t make it, either due to time constraints or a lack of transistors.
We are told that AMD has a clear internal roadmap for CPU microarchitecture design over the next few generations. As long as we don’t stay for so long on 14nm similar to what we did at 28/32nm, with IO updates over the coming years, a competitive clock-for-clock product (even to Broadwell) with good efficiency will be a welcome return.
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EchoWars - Thursday, March 2, 2017 - link
No, apparently the failure was in your education, since it's obvious you did not read the article.Notmyusualid - Friday, March 3, 2017 - link
Ha...sharath.naik - Thursday, March 2, 2017 - link
I think you missed the biggest news in this information dump. The TDP is the biggest advantage amd has. Which means that for 150watt server cpu. they should be able to cram a lot more cores than intel will be able to.Meteor2 - Friday, March 3, 2017 - link
^^^This. I think AMD's strength with Zen is going to be in servers.Sttm - Friday, March 3, 2017 - link
Yeah I can see that.UpSpin - Thursday, March 2, 2017 - link
According to a german site, in games, Ryzen is equal (sometimes higher, sometimes lower) to the Intel i7-6900K in high resolution games (WQHD). Once the resolution is set very low (720p) the Ryzen gets beaten by the Intel processor, but honestly, who cares about low resolution? For games, the probably best bet would be the i7-7700K, mainly because of the higher clock rate, for now. Once the games get better optimized for 8 cores, the 4-core i7-7700K will be beaten for sure, because in multi-threaded applications Ryzen is on par with the twice expensive Intel processor.I doubt it makes sense to buy the Core i7-6850K, it has the same low turbo boost frequency the 6900K has, thus low single threaded performance, but at only 6 cores. So I expect that it's the worst from both worlds. Poor multi-threaded performance compared to Ryzen, poor single threaded performance compared to i7-7700K.
We also have to see how well Ryzen can get overclocked, thus improving single core performance.
fanofanand - Thursday, March 2, 2017 - link
That is a well reasoned comment. Kudos!ShieTar - Thursday, March 2, 2017 - link
Well, the point of low-resolution testing is, that at normal resolutions you will always be GPU-restricted. So not only Ryzen and the i7-6900K are equal in this test, but so are all other modern and half-modern CPUs including any old FX-8...The most interesting question will be how Ryzen performs on those few modern games which manage to be CPU-restricted even in relevant resolutions, e.g. Battlefield 1 Multiplayer. But I think it will be a few more days, if not weeks, until we get that kind of in-depth review.
FriendlyUser - Thursday, March 2, 2017 - link
This is true, but at the same time this artificially magnifies the differences one is going to notice in a real-world scenario. I saw reviews with a Titan X at 1080p, while many will be playing 1440p with a 1060 or RX480.The test case must also approximate real life.
khanikun - Friday, March 3, 2017 - link
They aren't testing to show what it's like in real life though. The point of testing is to show the difference between the CPUs. Hence why they are gearing their benchmarking to stress the CPU, not other portions of the system.