Rambus has developed a comprehensive PCIe 5.0 and CXL interface solution for chips built using 7 nm process technologies. The interface is now available for licensing by SoC designers and will enable them to bring PCIe 5.0/CXL-supporting hardware to the market faster. Rambus’ PCIe 5.0 solution includes a controller core originally developed by Northwest Logic (which was recently acquired by Rambus) and is backwards compatible with PCIe 2.0, PCIe 3.0 and PCIe 4.0, as well as a PHY that also supports CXL. The solution supports 32 GT/s per lane data transfer rate and is designed for advanced 7 nm FinFET process technologies. Besides the IP itself, Rambus will also offer design, integration, and support services to speed up the development process. Rambus believes that its PCIe...
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