GDDR6

Cadence has announced that it has successfully taped out its GDDR6 IP on Samsung’s 7LPP fabrication process. The new building blocks should enable developers of various chips to be made using 7LPP and quickly and easily integrate support of GDDR6 memory into their SoCs. Cadence’s GDDR6 IP solution includes the company’s Denali memory controller, physical interface, and verification IP. The controller and PHY are rated to handle up to 16 Gbps data transfer rates per pin and feature a low bit-error rate (BER) feature that decreases retries on the memory bus to cut-down latency and therefore ensure a greater memory bandwidth. The IP package is available as Cadence’s reference design that allows SoC developers to quickly replicate implementation that the IP designer used for its...