Intel recently released a new version of its document for software developers revealing some additional details about its upcoming Xeon Scalable ‘Cooper Lake-SP’ processors. As it appears, the new CPUs will support AVX512_BF16 instructions and therefore the bfloat16 format. Meanwhile, the main intrigue here is the fact that at this point AVX512_BF16 seems to be only supported by the Cooper Lake-SP microarchitecture, but not its direct successor, the Ice Lake-SP microarchitecture.
In a publicly available document, found by an eagle-eyed user on Twitter, Cisco has revealed some details about the future Whitley Platform and Barlow Pass: the set of technologies...21 by Ian Cutress on 2/5/2019
As part of Intel's Datacenter summit, we were given an opportunity to sit down with Lisa Spelman, VP of Intel’s Data Center Group and General Manager of Xeon Products...41 by Ian Cutress on 8/15/2018
At its Data-Centric Innovation Summit in Santa Clara today, Intel unveiled its official Xeon roadmap for 2018 – 2019. As expected, the company confirmed its upcoming Cascade Lake, Cooper...55 by Ian Cutress & Anton Shilov on 8/8/2018
Earlier this year Intel confirmed that it would delay mass production of 10nm CPUs to 2019 due to issues with yields, but did not elaborate on when in 2019...50 by Anton Shilov on 7/26/2018
Recently a Chinese university has published a collection of slide-decks from various companies covering a server/HPC event. Among the slides, Intel had a seemingly longer comprehensive presentation describing Intel’s...19 by Anton Shilov on 7/25/2018