Integrated Memory Controller & North Bridge (continued)

The initial processors based on the Hammer architecture will feature either a 64-bit or 128-bit DDR SDRAM DCT. This DCT can support clock speeds of 100, 133 or 166MHz for DDR200, DDR266 or DDR333 SDRAM support. AMD has hinted very strongly that the replacement for a DDR based DCT would be a DDR-II based solution in later versions of Hammer based processors.

Memory Bandwidth Comparison
Memory Type
64-bit DCT
128-bit DCT
DDR200
1.6GB/s
3.2GB/s
DDR266
2.1GB/s
4.2GB/s
DDR333
2.7GB/s
5.4GB/s

The fact that the memory controller is on the CPU die itself also means that memory accesses scale directly with clock speed since the data doesn't need to traverse the FSB before getting to the CPU. The example AMD gave at MPF was of a theoretical 2GHz Hammer processor whose memory access latency was 12ns (see right for Hammer pipeline). Obviously that's not taking into account the time it takes to actually get data from memory, but it's much faster than going through an external North Bridge before getting to main memory.

That's all great, but we still haven't answered the question of how AMD plans on improving IPC - actually, we have. By getting data from memory to the CPU much faster, the Hammer's execution units will be able to stay filled much better than the Athlon was able to which results in an increase in overall IPC.

And again, an integrated memory controller removes one of the major roles of the external North Bridge. AMD took this one step further and actually integrated a North Bridge on the CPU die as well. The only thing that remains of the conventional external North Bridge is an AGP controller. This should pretty much eliminate any major performance issues stemming from the chipsets that the Hammer is paired with; it will also make motherboard manufacturers happier since routing traces to/from the CPU and memory will be vastly simplified.

Below you'll see an example of what a single processor Hammer system would look like:

As you can tell from the picture, the AGP 8X controller is the only other chip that the chipset manufacturer has to provide outside of the South Bridge. The AGP 8X controller connects to the Hammer processor via a HyperTransport link. It is possible that a chipset manufacturer could produce a single chip that would house all of the functions of a conventional South Bridge along with the AGP 8X controller to provide for a very simple and cost effective Hammer motherboard layout.

Another thing to take away from this diagram is the fact that you only see two memory banks stemming off of the Hammer processor. AMD has indicated to us that single processor desktop Hammer systems will support a maximum of 2 unbuffered DIMMs.

Integrated Memory Controller & North Bridge Vastly Improved Branch Predictor
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  • chowmanga - Tuesday, February 2, 2010 - link

    Anand, the link on page 2 leading to the discussion on the 64bit extension of the x86 is broken. Is there any way to read it? Reply

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