AMD's Hammer Architecture - Making Sense of it All

Multiprocessing

Although the Hammer was designed as a top to bottom solution for the highest end servers down to the smallest notebooks, it's clear that the majority of its design choices were inspired by the workstation/server nature of the CPU. Case in point would be Hammer's multiprocessing capabilities.

A Hammer with three Hyper Transport links

One of the biggest problems with designing and validating multiprocessor platforms is that the chipsets especially when dealing with a point to point bus protocol like the Athlon's EV6, are very difficult to design and implement on a board. The Hammer obviously doesn't use the EV6 bus (it uses AMD's own Hyper Transport) but it solves this issue of MP implementation by including up to two more Hyper Transport (HT) connects on each processor. You'll remember that one HT connect is used to interface with an external AGP 8X controller; the other two HT connects can be used to interface to up to two other processors.

Each processor has its own memory controller but to the OS and applications the memory is a unified array of memory. If a CPU is attempting to access memory controlled by another CPU, the read instruction is passed along from CPU to CPU until it finds the CPU with control of the memory and then it is sent to the CPU that requested it.

Each of the HT links and the memory controller are connected to a crossbar arbiter logic that handles the juggling of all of these requests coming from other CPUs and other logic outside of the CPU. Again the beauty of this is that the performance of the crossbar controller scales with clock speed meaning that the faster the CPU gets, the quicker the crossbar controller can move data between the various HT links and the memory controller. This is a welcome departure from the fixed frequency FSB in conventional systems that does not increase as CPU clock speed goes up.

The Multiprocessing Capabilities of Hammer
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This method of setting up MP systems without extraordinary requirements on the external chipsets has the potential of finally bringing 2P solutions down to the desktop level. While this may be a stretch, it does seem very plausible given the MP architecture of Hammer.