More than just a die shrink

The 0.13-micron Pentium III has specs that are virtually identical to the 0.18-micron Coppermine based Pentium IIIs.  They both have the same amount of cache (32KB L1, 256KB L2) and run off of the 133MHz FSB.  There are a couple of changes that were made to the Tualatin core that set it apart from the Coppermine it is replacing.

On the compatibility side, the Tualatin requires a new chipset because of its use of a lower voltage clocking specification.  Since the release of the Pentium Pro, all Intel P6 processors have used Gunning Transceiver Logic+ (GTL+) technology for their FSB.  The GTL+ implementation actually changed slightly from the Pentium Pro to the Pentium II/III, and thus the latter implement what is known as the Assisted Gunning Transceiver Logic+ (AGTL+) bus.  Both of these FSBs use 1.5V signaling; however, the Tualatin uses a lower voltage bus that runs at 1.25V.  More specifically, the Tualatin uses AGTL signaling that unfortunately requires a new chipset with support for 1.25V AGTL signaling instead of 1.5V AGTL+ signaling.  The Tualatin also supports single-ended and differential bus clocking schemes (whereas the Coppermine Pentium III only used single-ended clocking).  It is unclear whether the current 1.13GHz and 1.2GHz Tualatins use single-ended or differential clocking, but the main purpose for using a differential bus clocking scheme is to reduce Electromagnetic Interference (EMI) associated with higher clock speeds.  The Pentium 4 also uses differential clocking. 

Because it is manufactured on a smaller process, the Tualatin requires much less power than the Coppermine core.  The VRM 8.4 specification that was used by the Coppermine unfortunately only provided support for voltages in 0.05V increments using four VID pins (VID0 – VID3).  In order to provide support for smaller voltage steppings, the Tualatin requires a new VRM specification, VRM 8.5 that adds two additional pins: VID25mv and VTT_PWRGD.  The VID25mv pin works in conjunction with the four original VID pins in order to allow for 0.025V voltage increments.  The VTT_PWRGD pin requires a 1.25V input; if either of these two pins isn’t properly connected then the system will not boot.  This means that the Tualatin Pentium IIIs will not work on current motherboards.  We will address motherboard/chipset issues later in the review.

In terms of performance, the Tualatin offers one advantage over the Coppermine core in that it features Data Prefetch Logic (DPL).  The Pentium 4 has a similar feature that Intel simply called Hardware Prefetch.  Data Prefetch Logic looks at data access patterns and uses available FSB bandwidth to “prefetch” data into the processor’s L2 cache.  In the event that the DPL predicts correctly, the CPU can now get to the data that is already in its L2 cache instead of having to wait for it to come from main memory, which is considerably slower.  If DPL incorrectly predicts data there is no performance penalty.  AMD’s Athlon 4 (Palomino) core also offers similar functionality. 

Unfortunately, the Tualatin’s DPL is not as useful as similar functions in the Athlon 4 and Pentium 4 because the Tualatin is still stuck with only a 133MHz FSB.  The 64-bit AGTL FSB is only capable of a peak theoretical maximum of 1.06GB/s of bandwidth, while the Athlon 4 and Pentium 4 have 2.1GB/s and 3.2GB/s of FSB bandwidth, respectively.  The effectiveness of the Tualatin’s DPL is thus reduced because it does not have as much FSB bandwidth, but that also means that at higher overclocked FSB frequencies, the Tualatin will benefit much more than the Coppermine Pentium III did. 

Other than those two changes, the desktop Tualatin-based Pentium III carries an identical feature set to the Coppermine that it’s replacing. 

Index Cool Runnings: The Intel Bobsled Team

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