IDF Spring 2005 - Predicting Future CPU Architecture Trendsby Anand Lal Shimpi on March 3, 2005 7:43 PM EST
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We've come across a lot of information about the future of Intel architectures and platforms during these past three days at IDF. We've taken this opportunity to summarize it as best as we can, so let's get started.
More thoughts on Stacked DRAM
Our own Johan De Gelas caught up with Justin Rattner after his keynote to get some more information about stacked die and wafer technology:
1) Current Intel research estimates that about 256MB of memory can be stacked on top of a CPU (die stacking). A huge latency reduction is the result, but if you need more memory you have to go off die of course.
2) Different thermal expansion between the layers might of course ruin the chip. Intel is looking into this but Justin believes that it is not going to stop the stacked die show.
3) Right now stacked die is obviously in its infancy, they still have to move to the next step: one memory chip on top the other.
We're quite excited about the possibility of stacked DRAM although it will definitely be a long time before we see it productized.
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IntelUser2000 - Friday, March 4, 2005 - link"why would you make a feature on a cpu that can only be enabled later anyways?"
It may not make sense but apparently Pentium 4 had hyperthreading disabled for even Willamette. There are talks about unused "dark transistors" in Prescott. Why would they do that? Maybe because its not feasible, or easy, or cheap enough, and they want to enable it later. Like if Willamette had HT disabled, the performance degrade would have been significant, unlike today, which is negligible. But its easier to enable when its already there don't you think?
"I thought we were talking about ways of increasing bandwidth to the cpu -- eg. intel does it by increasing the ram standard (ddr333 to ddr400), amd has now chosen to have the on die memory controller so as faster HTT will increase bandwidth between cpu and everything else"
Specifically, bandwidth between dual processor and multi-processor and/or I/O. We are talking about desktops here so its only I/O. The CPU only need to talk to the memory controller for memory banwidth, and its integrated so it doesn't need HTT increase.
You are kinda saying that if bus speeds increase in Pentium 4's, L2 cache bandwidth increases. That doesn't make sense at all. http://www.amd.com/us-en/Processors/ProductInforma...
It even says at AMD for HTT: A system bus that uses HyperTransport technology for high-speed I/O COMMUNICATION.
Houdani - Friday, March 4, 2005 - link/snicker People talking to themselves is always good for a chuckle.
ncage - Friday, March 4, 2005 - link#20. I do agree with you that this would be a nightmare to code for unless they make the compiler so good that it does a majoritiy of the work for you which i can't imagine the compiler being THAT good. That would mean lots and lots of multithreaded programming which gets VERY complex. There are usually a few things you can spawn a new thread and process stuff in the background but for most applications, more than a few threads are not needed and deciding areas of your application that could be sped up with more threads becomes VERY complex. Take a for loop. Maybe every iteration in your for loop could be handled by a seperate process but what happenes if they are handled in order? What if you have the 3rd result before you have the 1st. This is a relatively simple example of course. Multithreaded programming becomes quite complex. High Multiprocessing becomes very useful in complex scientific appliations though. I also thing it would be quite useful in games
On a side note i want to know what you have programmed like this? IF you have programmed something like i will be quite impressed.
fitten - Friday, March 4, 2005 - linkWell... we have yet to see whether Cell will make it out of PS3s and IBM servers, though. Cell will be too complicated to program for regular programmers (I've programmed similar systems in the past) and Sony's paper launch claims that they've solved problems that no one has been able to solve yet... so... forgive me if I don't hold my breath waiting for Cell.
Warder45 - Friday, March 4, 2005 - linkYeah but now they have competition with CELL to get them moving on SPH.
mrmorris - Friday, March 4, 2005 - link"Intel has spoken a bit about including special purpose hardware in their forthcoming processors..."
Yeah well, that's what they 6said back in the MMX days some 3600MHz ago!!
xsilver - Friday, March 4, 2005 - link"Dude, HTT is not memory standard, that's the link for the I/O, or in case of servers, communication between CPUs, get your facts straight. "
I thought we were talking about ways of increasing bandwidth to the cpu -- eg. intel does it by increasing the ram standard (ddr333 to ddr400), amd has now chosen to have the on die memory controller so as faster HTT will increase bandwidth between cpu and everything else
"Not exactly free since you need to buy the CPU, you can't just enable on current CPUs can you? :). "
intel has the same thing, except you change the mobo instead of the cpu? how many people change the mobo without changing the cpu == answer, nobody .... why would you make a feature on a cpu that can only be enabled later anyways? its like your dad handing you the keys to a ferrari but then says, you can only drive it when you're 18 sonny boy :) ... why not just buy you the ferrari when you're 18?..... oh wait -- didnt intel just do it with their 64bit instructions on the prescott?
from a performance perspective I still cant see a good argument for why intel is leaving out the on die controller.... its all economics of making more money from chipset sales
sphinx - Friday, March 4, 2005 - linkI agree #11
I think it is time to dump x86 altogether. Let's face it, Intel and AMD are still using the x86 architecture as a base for their new processors. I want to know if the CELL processor will change computing as we know it.
ceefka - Friday, March 4, 2005 - linkDedicated logic is nice when you can update it by flash (like BIOS). That can already be done by using FPGAs and CPLDs (like Xilinx). If too much becomes dedicated in a fixed way, without being low-cost upgradable the PC loses its versatility and attractiveness altogether.
Can anyone remember what a PC was like ten years back in 1995? Who would have predicted then that we would have 64-bit capable CPU's on the brink of going dual core, 4GB capable mainboards, 300GB HDDs, LCD screens, and actually affordable RAM?
When Intel adopts all these memory techniques so fast it's only logical that they are hesitant to produce a CPU with integrated mem controller.
256MB on die RAM? That will be one expensive MF!
IntelUser2000 - Friday, March 4, 2005 - link"intel's reasoning doesn't make sense. they seem make people change mobos, not because of differing ram standards, but because they change cpu socket so damn often."
Well, it makes sense at server side, specifically Xeon MP and Itanium, and according to some news that's what they are gonna do, since FB-DIMM will allow changing standards without changing chipsets or chip.
" the memory controller on the AMD64 has already been updated from HTT800mhz to HTT1000mhz.... and can be continually revised and just introduced on newer steppings of the same cpu's.... eg. amd's forthcoming "e" spec with sse3, 4x ddr3200 support and other stuff for free"
Dude, HTT is not memory standard, that's the link for the I/O, or in case of servers, communication between CPUs, get your facts straight.
We don't know what's the max speed grade the memory controller on A64 will support. But the thing is if you want better memory standards than what the memory controller is capable of, you need newer versions, in this case newer CPU. Of course this does not apply to S423 to S478 and S478 to S775.
"amd's forthcoming "e" spec with sse3, 4x ddr3200 support and other stuff for free"
Not exactly free since you need to buy the CPU, you can't just enable on current CPUs can you? :).
SSE3 is not related to integrated memory controller, 4xDDR3200 support was there already.