The Skylake CPU Architecture

As with any new Intel architecture, the devil is in the details. Previously at AnandTech we have been able to provide deep dives into what exactly is going on in the belly of the beast, although the launch of Skylake has posed a fair share of problems.

Nominally we rely on a certain amount of openness from the processor/SoC manufacturer in providing low level details that we can verify and/or explain. In the past, this information has typically been provided in advance of the launch by way of several meetings/consultations with discussions talking to the engineers. There are some things we can probe, but others are like a black box. The black box nature of some elements, such as Qualcomm’s Adreno graphics, means that it will remain a mystery until Pandora’s box is opened.

In the lead up to the launch of Intel’s Skylake platform, architecture details have been both thin on the ground and thin in the air, even when it comes down to fundamental details about the EU counts of the integrated graphics, or explanations regarding the change in processor naming scheme. In almost all circumstances, we’ve been told to wait until Intel’s Developer Forum in mid-August for the main reason that the launch today is not the full stack Skylake launch, which will take place later in the quarter. Both Ryan and I will be at IDF taking fastidious notes and asking questions for everyone, but at this point in time a good portion of our analysis comes from information provided by sources other than Intel, and while we trust it, we can't fully verify it as we normally would.

As a result, the details on the following few pages have been formed through investigation, discussion and collaboration outside the normal channels, and may be updated as more information is discovered or confirmed. Some of this information is mirrored in our other coverage in order to offer a complete picture in each article as well. After IDF we plan to put together a more detailed architecture piece as a fundamental block in analyzing our end results.

The CPU

As bad as it sounds, the best image of the underlying processor architecture is the block diagram:

From a CPU connectivity standpoint, we discussed the DDR3L/DDR4 dual memory controller design on the previous page so we won’t go over it again here. On the PCI-Express Graphics allocation side, the Skylake processors will have sixteen PCIe 3.0 lanes to use for directly attached devices to the processor, similar to Intel's previous generation processors. These can be split into a single PCIe 3.0 x16, x8/x8 or x8/x4/x4 with basic motherboard design. (Note that this is different to early reports of Skylake having 20 PCIe 3.0 lanes for GPUs. It does not.)

With this, SLI will work up to x8/x8. If a motherboard supports x8/x4/x4 and a PCIe card is placed into that bottom slot, SLI will not work because only one GPU will have eight lanes. NVIDIA requires a minimum of PCIe x8 in order to enable SLI. Crossfire has no such limitation, which makes the possible configurations interesting. Below we discuss that the chipset has 20 (!) PCIe 3.0 lanes to use in five sets of four lanes, and these could be used for graphics cards as well. That means a motherboard can support x8/x8 from the CPU and PCIe 3.0 x4 from the chipset and end up with either dual-SLI or tri-CFX enabled when all the slots are populated.

DMI 3.0

The processor is connected to the chipset by the four-lane DMI 3.0 interface. The DMI 3.0 protocol is an upgrade over the previous generation which used DMI 2.0 – this upgrade boosts the speed from 5.0 GT/s (2GB/sec) to 8.0 GT/s (~3.93GB/sec), essentially upgrading DMI from PCIe 2 to PCIe 3, but requires the motherboard traces between the CPU and chipset to be shorter (7 inches rather than 8 inches) in order to maintain signal speed and integrity. This also allows one of the biggest upgrades to the system, chipset connectivity, as shown below in the HSIO section.

CPU Power Arrangements

Moving on to power arrangements, with Skylake the situation changes as compared to Haswell. Prior to Haswell, voltage regulation was performed by the motherboard and the right voltages were then put into the processor. This was deemed inefficient for power consumption, and for the Haswell/Broadwell processors Intel decided to create a fully integrated voltage regulator (FIVR) in order to reduce motherboard cost and reduce power consumption. This had an unintended side-effect – while it was more efficient (good for mobile platforms), it also acted as a source of heat generation inside the CPU with high frequencies. As a result, overclocking was limited by temperatures and the quality of the FIVR led to a large variation in results. For Skylake on the desktop, the voltage regulation is moved back into the hands of the motherboard manufacturers. This should allow for cooler processors depending on how the silicon works, but it will result in slightly more expensive motherboards.

A slight indication of this will be that some motherboards will go back to having a large amount of multiplexed phases on the motherboard, and it will allow some manufacturers to use this as a differentiating point, although the usefulness of such a design is sometimes questionable.

Also Launching Today: Z170 Motherboards, Dual Channel DDR4 Kits Skylake's iGPU: Intel Gen9
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  • MrBungle123 - Sunday, August 9, 2015 - link

    In the Athlon 64 days, yes, AMD had a better product but the cold hard truth behind the curtain was that AMD didn't have the manufacturing capacity to supply everyone that Intel was feeding chips to. Reply
  • silverblue - Thursday, August 6, 2015 - link

    A "tweaked 8-core Ph2"? Putting aside the fact that significant changes would've been required to the fetch and retire hardware (the integer units themselves were very capable but were underutilised), a better IMC and all the modern instruction sets that K10 didn't support, AMD had already developed its replacement. It probably would've buried them to have to shelve Bulldozer (twice, it turns out) and redevelop what was essentially a 12-year old micro-architecture.

    AMD were under pressure to deliver Bulldozer hence the cutting of corners and the decision to go with GF's poor 32nm process as they simply didn't have any alternative (plus I imagine they were promised far more than GF could deliver). Phenom II was not enough against Nehalem, let alone Sandy Bridge.

    Blaming Intel doesn't help either as AMD couldn't exactly saturate the market with their products even when they were fabbing them themselves, however I think the huge drop in mainstream CPU prices when Core 2 was released along with the huge price paid for ATi did more damage than any bribing of retailers and systems manufacturers.
    Reply
  • nikaldro - Wednesday, August 5, 2015 - link

    40% over excavator, with 8 cores, good clockspeeds and good pricing doesn't sound that bad. I'll wait till Zen comes out, then decide. Reply
  • Spoelie - Thursday, August 6, 2015 - link

    IPC difference between piledriver and skylake amounts to 80%... Lets hope excavator's IPC is better than anticipated and 40% is sandbagging it a bit.

    Given AMD's track record of overpromising and underdelivering, I'm afraid Zen will massively disappoint.
    Reply
  • Asomething - Thursday, August 6, 2015 - link

    Well it will only be behind by something like 15-25% if the difference between piledriver and skylake is 80% since piledriver to excavator is supposed to be a good 20% jump. If amd can manage to catchup in any meaningful way and make chips that can touch 5ghz then things might turn out ok. Reply
  • mapesdhs - Thursday, August 6, 2015 - link

    Catchup will not be good enough. They need to be usefully competitive to pull people away from Intel into a platform switch, especially business, who have to think about this sort of thing for the long haul, and AMD's track record has been pretty woeful in this regard. I hope they can bring it to the table with Zen, but I'll believe it when I see it. Highly unlikely Intel isn't planning to either splat its prices or shove up performance, etc., if they need to when Zen comes out, especially for consumer CPUs. We know what's really possible based on how many cores, TDP, clock rates, etc. are used for the XEONs, but that potential just hasn't been put into a consumer chip yet.
    Remember, Intel could have released an 8-core for X79, but they didn't because there was no need; indeed the 3930K *is* an 8-core, just with 2 cores disabled (read the reviews). Ever since then, again and again, Intel has held back what it's perfectly capable of producing if it wanted to. The low clock of the 5960X is yet another example, it could easily be much higher.
    Reply
  • MapRef41N93W - Friday, August 7, 2015 - link

    You're assuming it's going to be a flat 40% over Excavator and not a best case scenario 40% (like every single AMD future performance projection always is...). It's more than likely a flat 20% IPC increase which puts it even behind Nehalem IPC wise.

    Top off the fact that it's AMD's first FinFET part (look at the penalty Intel paid in clockspeed with the transition to FinFET with IB/HW) and a transition to a new scalable uARCH (again look at the clockspeed hit Intel took when going from Netburst to scalable core arch, very similar to what AMD is doing now actually) and I can see Zen parts clocking horribly on top of that. Being on a Samsung node that is designed with low power in mind won't help their case either.

    You may get an 8 core Zen part for $300-$400 but it probably won't clock worth a damn and end up at 3.5-4GHz on average. So it would be a much worse choice than a 5820k for most people.
    Reply
  • mapesdhs - Wednesday, August 12, 2015 - link

    Btw, I wasn't assuming anything about Zen, I really haven't a clue how it'll compare to Intel's offerings of the day. I hope it's good, but with all that's happened before, I hope for the best but expect the worst, though I'd like to be wrong. Reply
  • Azix - Friday, August 21, 2015 - link

    You guys are being pretty negative on AMD. AMD tried to do an 8core chip on 32nm, maybe that was their mistake. The market wasn't even ready considering how long that way and where we are now. I do think intel got them pretty badly with their cheating

    The next processors are on a much better process. Based on the process alone we would expect a significant bit more performance than some seem willing to allow. Not to mention the original architecture was designed on a 32nm process. It's no surprise it would fall that far behind intel who is currently on 14nm. As time progresses though, those process jumps will take intel longer and longer. AMD will be much closer. Next year will be the first these two are on the same process (similar anyway). in a long while and it will last till at least 2017. AMD should be able to pick up some CPU sales next year and hopefully return to profitability. Intel also enjoys ddr4 support.

    Stop pushing old 32nm architectures and crappy motherboards.
    Reply
  • SkOrPn - Tuesday, December 13, 2016 - link

    Well if you were paying attention to AMD news today, maybe you partially got your answer finally. Jim Keller yet again to the rescue. Ryzen up and take note... AMD is back... Reply

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