The Skylake CPU Architecture

As with any new Intel architecture, the devil is in the details. Previously at AnandTech we have been able to provide deep dives into what exactly is going on in the belly of the beast, although the launch of Skylake has posed a fair share of problems.

Nominally we rely on a certain amount of openness from the processor/SoC manufacturer in providing low level details that we can verify and/or explain. In the past, this information has typically been provided in advance of the launch by way of several meetings/consultations with discussions talking to the engineers. There are some things we can probe, but others are like a black box. The black box nature of some elements, such as Qualcomm’s Adreno graphics, means that it will remain a mystery until Pandora’s box is opened.

In the lead up to the launch of Intel’s Skylake platform, architecture details have been both thin on the ground and thin in the air, even when it comes down to fundamental details about the EU counts of the integrated graphics, or explanations regarding the change in processor naming scheme. In almost all circumstances, we’ve been told to wait until Intel’s Developer Forum in mid-August for the main reason that the launch today is not the full stack Skylake launch, which will take place later in the quarter. Both Ryan and I will be at IDF taking fastidious notes and asking questions for everyone, but at this point in time a good portion of our analysis comes from information provided by sources other than Intel, and while we trust it, we can't fully verify it as we normally would.

As a result, the details on the following few pages have been formed through investigation, discussion and collaboration outside the normal channels, and may be updated as more information is discovered or confirmed. Some of this information is mirrored in our other coverage in order to offer a complete picture in each article as well. After IDF we plan to put together a more detailed architecture piece as a fundamental block in analyzing our end results.

The CPU

As bad as it sounds, the best image of the underlying processor architecture is the block diagram:

From a CPU connectivity standpoint, we discussed the DDR3L/DDR4 dual memory controller design on the previous page so we won’t go over it again here. On the PCI-Express Graphics allocation side, the Skylake processors will have sixteen PCIe 3.0 lanes to use for directly attached devices to the processor, similar to Intel's previous generation processors. These can be split into a single PCIe 3.0 x16, x8/x8 or x8/x4/x4 with basic motherboard design. (Note that this is different to early reports of Skylake having 20 PCIe 3.0 lanes for GPUs. It does not.)

With this, SLI will work up to x8/x8. If a motherboard supports x8/x4/x4 and a PCIe card is placed into that bottom slot, SLI will not work because only one GPU will have eight lanes. NVIDIA requires a minimum of PCIe x8 in order to enable SLI. Crossfire has no such limitation, which makes the possible configurations interesting. Below we discuss that the chipset has 20 (!) PCIe 3.0 lanes to use in five sets of four lanes, and these could be used for graphics cards as well. That means a motherboard can support x8/x8 from the CPU and PCIe 3.0 x4 from the chipset and end up with either dual-SLI or tri-CFX enabled when all the slots are populated.

DMI 3.0

The processor is connected to the chipset by the four-lane DMI 3.0 interface. The DMI 3.0 protocol is an upgrade over the previous generation which used DMI 2.0 – this upgrade boosts the speed from 5.0 GT/s (2GB/sec) to 8.0 GT/s (~3.93GB/sec), essentially upgrading DMI from PCIe 2 to PCIe 3, but requires the motherboard traces between the CPU and chipset to be shorter (7 inches rather than 8 inches) in order to maintain signal speed and integrity. This also allows one of the biggest upgrades to the system, chipset connectivity, as shown below in the HSIO section.

CPU Power Arrangements

Moving on to power arrangements, with Skylake the situation changes as compared to Haswell. Prior to Haswell, voltage regulation was performed by the motherboard and the right voltages were then put into the processor. This was deemed inefficient for power consumption, and for the Haswell/Broadwell processors Intel decided to create a fully integrated voltage regulator (FIVR) in order to reduce motherboard cost and reduce power consumption. This had an unintended side-effect – while it was more efficient (good for mobile platforms), it also acted as a source of heat generation inside the CPU with high frequencies. As a result, overclocking was limited by temperatures and the quality of the FIVR led to a large variation in results. For Skylake on the desktop, the voltage regulation is moved back into the hands of the motherboard manufacturers. This should allow for cooler processors depending on how the silicon works, but it will result in slightly more expensive motherboards.

A slight indication of this will be that some motherboards will go back to having a large amount of multiplexed phases on the motherboard, and it will allow some manufacturers to use this as a differentiating point, although the usefulness of such a design is sometimes questionable.

Also Launching Today: Z170 Motherboards, Dual Channel DDR4 Kits Skylake's iGPU: Intel Gen9
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  • SIDESIDE - Sunday, August 9, 2015 - link

    Actually, you are a child. As for you throwing gasoline on the fire here in the intel vs. amd debate. THERE IS NO DEBATE, intel is literally twice as efficient and powerful as amd, and why wouldn't it? they are 2twice as old a company and have a lunch budget bigger than amd's R&D budget. amd's are a budget line of processors, so you buy budget cause money is tight, good for you. I run a video company and will gladly pay and extra $150 for twice as fast rendering all year. I hope AMD the best because competition is ALWAYS a good thing. but you, prisonerX clearly have your head up your A** Reply
  • medi03 - Thursday, August 6, 2015 - link

    They did that quite a while ago. Reply
  • Artas1984 - Thursday, August 6, 2015 - link

    WELL SAID!!! Reply
  • SkOrPn - Tuesday, December 13, 2016 - link

    Zen appears to be matching the $1050 i7-6900K. I would say that is far better then Nehalem. Reply
  • mmrezaie - Wednesday, August 5, 2015 - link

    Zen needs more than 40% improvement to be competent, but I am hoping as well. Reply
  • mdriftmeyer - Wednesday, August 5, 2015 - link

    The word you're looking for is competitive. Reply
  • Peichen - Wednesday, August 5, 2015 - link

    Competent, competitive. AMD is neither at the moment so both of you are correct. Reply
  • prisonerX - Thursday, August 6, 2015 - link

    Actually AMD is very competent given how much money they have to work with. AMD would be much more competitive too now if it were not for Intel's well documented illegal practices against AMD.

    It's like a thief robbed your home and you're praising the fact that it's great that you can go to the pawn shop and buy what he stole from you.
    Reply
  • mapesdhs - Thursday, August 6, 2015 - link

    Wow, blaming years of terrible decisions on Intel... that's a new one. It wasn't Intel that made AMD adopt automated design tools, or ignore the much easier, faster and obvious option of releasing a tweaked 8-core Ph2. AMD has made massive losses year after year. Their debts are awful. Blaming all this on Intel is just nuts. Reply
  • medi03 - Thursday, August 6, 2015 - link

    Yeah. Blaming Intel that HP didn't want to use FASTER AMD CPUs FOR FREE, fearing Intel's illegal revenge is just nuts.

    AMD Athlon 64's beat Intel in all regards, they were faster, cheaper and less power hungry. Yet Intel was selling several times more Prescotts,

    Not being able to profit even in a situation when you have superior product (despite much modest R&D budget), yeah, why blame intel.
    Reply

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