AMD Launches Carrizo: The Laptop Leap of Efficiency and Architecture Updates
by Ian Cutress on June 2, 2015 9:00 PM ESTAMD Secure Processor
One of the final pieces in the puzzle is AMD’s Secure Processor, which they seemed to have called the PSP. The concept of the security processor has evolved over time, but the premise of a locked down area to perform sensitive work that is both hidden and cryptographically sealed appeals to a particular element of the population, particularly when it comes to business.
AMD’s PSP is based around a single 32-bit ARM Cortex-A5, with its own isolated ROM and SRAM but has access to system memory and resources. It contains logic to deal with the x86 POST process but also features a cryptographic co-processor.
ARM has been promoting TrustZone for a couple of years now, and AMD has been tinkering with their Secure Processor proposition for almost as long although relatively few explanations from AMD outside ‘it is there’ have come forward.
Final Thoughts
Sometimes a name can inspire change. Carrizo isn’t one of those names, and when hearing the words ‘AMD’s notebook processor’, those words have not instilled much hope in the past, much to AMD’s chagrin no doubt. Despite this, we come away from Carrizo with a significantly positive impression because this feels more than just another Bulldozer-based update.
If you can say in a sentence ‘more performance, less power and less die area’, it almost sounds like a holy trifecta of goals a processor designer can only hope to accomplish. Normally a processor engineer is all about performance, so it takes an adjustment in thinking to focus more so on power, but AMD is promising this with Carrizo. Part of this will be down to the effectiveness of the high density libraries (which according to the slides should also mean less power or more performance for less die area) but also the implementation of the higher bandwidth encoder, new video playback pathway and optimization of power through the frequency planes. Doubling the L1 data cache for no loss in latency will have definite impacts to IPC, as well as the better prefetch and branch prediction.
Technically, on paper, all the blocks in play look exciting and every little margin can help AMD build a better APU. It merely requires validation of the results we have been presented along with a killer device to go along with it, something which AMD has lacked in the past and reviewers have had trouble getting their hands on. We are in discussions with AMD to get the sufficient tools to test independently a number of the claims, and to see if AMD’s Carrizo has potential.
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FlushedBubblyJock - Tuesday, June 9, 2015 - link
amazing how a critically correct comment turns into an angry ranting conspiracy from youBillyONeal - Wednesday, June 3, 2015 - link
This is a preview piece. They don't have empirical data because the hardware isn't in actual devices yet. Look at any of AT's IDF coverage and you'll see basically the exact same thing.Refuge - Wednesday, June 3, 2015 - link
nothing has been released yet. but it was announced. This is a news site, you think they are just going to ignore AMD's product announcement? That would be considered "Not doing their job"They go through the claims, explain them, try to see if they are plausible with what little information they have. I like these articles, it gives me something to digest while I wait for a in depth review, and when I go to read said review I know exactly what information I'm most interested in.
KaarlisK - Wednesday, June 3, 2015 - link
About adaptive clocking.Power is not saved by reducing frequency by 5% for 1% of the time.
Power is saved by reducing the voltage margin (increasing frequency at the same voltage) _all_ the time.
Also, when the voltage instability occurs, only frequency is reduced. The requested voltage, IMHO, does not change.
ingwe - Wednesday, June 3, 2015 - link
Interesting. That makes more sense for sure.name99 - Monday, June 8, 2015 - link
It seems like a variant of this should be widely applicable (especially if AMD have patents on exactly what they do). What I have in mind is that when you detect droop rather than dynamically change the frequency (which is hard and requires at least some cycles) you simply freeze the entire chip's clock at the central distribution point --- for one cycle you just hold everything at zero rather than transitioning to one and back. This will give the capacitors time to recover from the droop (and obviously the principle can be extended to freeze the clock for two cycles or even more if that's how long it takes for the capacitors to recover).This seems like it should allow you to run pretty damn close to the minimum necessary voltage --- basically all you now need is enough margin to ensure that you don't overdraw within a worst case single-cycle. But you don't need to provision for 3+ worst-case cycles, and you don't need the alternative of fancy check-point and recovery mechanisms.
KaarlisK - Wednesday, June 3, 2015 - link
About that power plane."In yet more effort to suction power out of the system, the GPU will have its own dedicated voltage plane as part of the system, rather than a separate voltage island requiring its own power delivery mechanism as before"
As I understand it, "before" = same power plane/island as other parts of the SoC.
Gadgety - Wednesday, June 3, 2015 - link
Great read and analysis given the fact that actual units are not available for testing.As a consumer looking for use of Carrizo beyond laptops, provided AMD releases it for consumers, it could be a nice living room HTPC/light gaming unit.
Laxaa - Wednesday, June 3, 2015 - link
I would buy a Dell XPS13-esque machine with this(i.e. high quality materials, good design and a high res screen)Will Robinson - Wednesday, June 3, 2015 - link
According to ShintelDK and Chizow...the above article results are from an Intel chip and AT have been paid to lie and say its Carrizo because their lives would have no meaning if it is a good product from AMD.