AMD Launches Carrizo: The Laptop Leap of Efficiency and Architecture Updates
by Ian Cutress on June 2, 2015 9:00 PM ESTAMD Secure Processor
One of the final pieces in the puzzle is AMD’s Secure Processor, which they seemed to have called the PSP. The concept of the security processor has evolved over time, but the premise of a locked down area to perform sensitive work that is both hidden and cryptographically sealed appeals to a particular element of the population, particularly when it comes to business.
AMD’s PSP is based around a single 32-bit ARM Cortex-A5, with its own isolated ROM and SRAM but has access to system memory and resources. It contains logic to deal with the x86 POST process but also features a cryptographic co-processor.
ARM has been promoting TrustZone for a couple of years now, and AMD has been tinkering with their Secure Processor proposition for almost as long although relatively few explanations from AMD outside ‘it is there’ have come forward.
Final Thoughts
Sometimes a name can inspire change. Carrizo isn’t one of those names, and when hearing the words ‘AMD’s notebook processor’, those words have not instilled much hope in the past, much to AMD’s chagrin no doubt. Despite this, we come away from Carrizo with a significantly positive impression because this feels more than just another Bulldozer-based update.
If you can say in a sentence ‘more performance, less power and less die area’, it almost sounds like a holy trifecta of goals a processor designer can only hope to accomplish. Normally a processor engineer is all about performance, so it takes an adjustment in thinking to focus more so on power, but AMD is promising this with Carrizo. Part of this will be down to the effectiveness of the high density libraries (which according to the slides should also mean less power or more performance for less die area) but also the implementation of the higher bandwidth encoder, new video playback pathway and optimization of power through the frequency planes. Doubling the L1 data cache for no loss in latency will have definite impacts to IPC, as well as the better prefetch and branch prediction.
Technically, on paper, all the blocks in play look exciting and every little margin can help AMD build a better APU. It merely requires validation of the results we have been presented along with a killer device to go along with it, something which AMD has lacked in the past and reviewers have had trouble getting their hands on. We are in discussions with AMD to get the sufficient tools to test independently a number of the claims, and to see if AMD’s Carrizo has potential.
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name99 - Saturday, June 6, 2015 - link
You are comparing a $400 laptop to a $1500 laptop and, what do you know, the $1500 laptop comes out better. What a surprise!The point is that in this space batteries have long been cheap and the energy efficiency nothing like at the higher end. Which means the work-life has been something like 3 hrs. If AMD shifts that to six hours with this chip, that's a massive improvement in the target space.
You're also making bad assumptions about why these laptops are bought. If you rely on your laptop heavily for your job, you buy a $1500 laptop. These machines are bought to act as light performance desk machines that are occasionally (but only occasionally) taken to a conference room or on a field trip.
name99 - Saturday, June 6, 2015 - link
AMD does not have infinite resources. This play makes sense.Intel is essentially operating by starting with a Xeon design point and progressively stripping things out to get to Broadwell-M, which means that Broadwell-M over-supplies this $400-$700 market. Meanwhile at the really low end, Intel has Atom.
AMD is seeing (correctly, I think) that there is something of a gap in the Intel line which they can cover AND that this gap will probably persist for some time --- Intel isn't going to create a third line just to fit that gap.
Krysto - Wednesday, June 3, 2015 - link
I might be ready to get into AMD, as AMD has a lot of innovation lately. But it still disappoints me greatly that they aren't able to adopt a more modern process node.If they launch their new high-performance CPU core next year as part of an APU that uses HBM memory and is at the very least on 16nm FinFET, I might get that instead of a Skylake laptop. HSA is pretty cool and one of the reasons I'd get it.
UtilityMax - Wednesday, June 3, 2015 - link
The Kaveri FX parts are still almost half as slow in IPC as a competing Intel Core i3 with the same TDP. Only in tests involving multithreaded apps that can load all four cores the FX parts are keeping up with the Core i3. Let's hope the Carrizo generation of APUs will improve this situation.silverblue - Thursday, June 4, 2015 - link
Without being an AMD apologist, I think the point was that single threaded performance was "good enough" for your usual light work which tends to be hamstrung by I/O anyway.There are two things that I need to see clarified about Carrizo, however:
1) Does Carrizo drop CPU frequency automatically when the GPU is being taxed? That's certainly going to be an issue as regards the comparison with an i3.
2) With the addition of AVX2, were there any architectural changes made to accommodate AVX2, for example a wider FlexFPU?
sonicmerlin - Tuesday, June 9, 2015 - link
Yup. I'll wait for the 14 nm Zen APUs with HBM. The performance leap (both CPU and GPU) should be truly massive.Phartindust - Thursday, June 4, 2015 - link
Dude your gettin a Dell with a AMD processor!When was the last time that happened?
Looks like @Dell loves #Carrizo, and will use @AMD once again. #AMDRTP http://www.cnet.com/au/news/dell-inspirion-amd-car... …
elabdump - Friday, June 5, 2015 - link
Don't forget that Intel gives you an non fixable NSA approved BIOS: http://mjg59.dreamwidth.org/33981.htmlpatrickjchase - Friday, June 5, 2015 - link
Ian, you appear to have confused I-cache and D-cache.You wrote: "The L1 data cache is also now an 8-way associative design, but with the better branch prediction when needed it will only activate the one segment required and when possible power down the rest".
This is of course gibberish. Branch prediction would help to predict the target set of an *instruction* fetch from the I-cache, but is useless for D-cache set prediction for the most part (I say "for the most part" because Brad Calder did publish a way-prediction scheme based on instruction address back in the 90s. It didn't work very well and hasn't been productized that I know of).
zodiacfml - Friday, June 5, 2015 - link
Imagine what they could with 14nm of this, probably at half the cost of a Core M with 60 to 70% CPU performance of the M, yet with better graphics at the same TDP.