AMD Launches Carrizo: The Laptop Leap of Efficiency and Architecture Updates

AMD Secure Processor

One of the final pieces in the puzzle is AMD’s Secure Processor, which they seemed to have called the PSP. The concept of the security processor has evolved over time, but the premise of a locked down area to perform sensitive work that is both hidden and cryptographically sealed appeals to a particular element of the population, particularly when it comes to business.

AMD’s PSP is based around a single 32-bit ARM Cortex-A5, with its own isolated ROM and SRAM but has access to system memory and resources. It contains logic to deal with the x86 POST process but also features a cryptographic co-processor.

ARM has been promoting TrustZone for a couple of years now, and AMD has been tinkering with their Secure Processor proposition for almost as long although relatively few explanations from AMD outside ‘it is there’ have come forward.

Final Thoughts

Sometimes a name can inspire change. Carrizo isn’t one of those names, and when hearing the words ‘AMD’s notebook processor’, those words have not instilled much hope in the past, much to AMD’s chagrin no doubt. Despite this, we come away from Carrizo with a significantly positive impression because this feels more than just another Bulldozer-based update.

If you can say in a sentence ‘more performance, less power and less die area’, it almost sounds like a holy trifecta of goals a processor designer can only hope to accomplish. Normally a processor engineer is all about performance, so it takes an adjustment in thinking to focus more so on power, but AMD is promising this with Carrizo. Part of this will be down to the effectiveness of the high density libraries (which according to the slides should also mean less power or more performance for less die area) but also the implementation of the higher bandwidth encoder, new video playback pathway and optimization of power through the frequency planes. Doubling the L1 data cache for no loss in latency will have definite impacts to IPC, as well as the better prefetch and branch prediction.

Technically, on paper, all the blocks in play look exciting and every little margin can help AMD build a better APU. It merely requires validation of the results we have been presented along with a killer device to go along with it, something which AMD has lacked in the past and reviewers have had trouble getting their hands on. We are in discussions with AMD to get the sufficient tools to test independently a number of the claims, and to see if AMD’s Carrizo has potential.