We covered the news of the first shipment of 64-bit ARMv8 processors in the HP Moonshot product line earlier this week. At ARM TechCon 2014, Applied Micro (APM) had a very interesting update to their 64-bit ARM v8 product line. They launched two SoC families, HeliX 1 and HeliX 2. Both of them are based on the X-Gene ARMv8 cores developed for servers, but appropriately scaled down to fit in the 8 W - 42 W TDP scenarios for the embedded market. The HeliX 1 is fabricated in a 40 nm process, while the HeliX 2 uses a 28 nm process. The latter uses the second generation X-Gene ARMv8 core.

Applied Micro has traditionally been a PowerPC house. In fact, we have evaluated their Catalina networked storage platform in the Thecus N2310 and looked at the previous generation PowerPC SoC in the Western Digital My Book Live. However, in 2010, Applied Micro obtained an architecture license for ARMv8 (the 64-bit ARM architecture). Understanding that PowerPC was in decline, Applied Micro decided to devote all development resources to ARMv8. As part of this deal, all product lines based on the PowerPC architecture are being migrated to ARMv8 under the HeliX family.

APM is hoping to get HeliX into the embedded market, with focus on communication and networking, imaging, storage and industrial computing verticals. They believe ARMv8 is the architecture of the future and had a number of companies (including Cisco, Netgear, Konica Minolta, Wind River and Canonical) voicing support for their strategy.

The two SoC product lines launched by APM yesterday were the APM887208-H1 (based on HeliX 1) and the APM887104-H2 (based on HeliX 2). The SoC block diagrams of both of these SoCs are provided below, along with a table summarizing and comparing the various aspects.

Applied Micro Helix Block Diagram

Applied Micro HeliX Family
  APM887208-H1 APM887104-H2
Cores 4 or 8 ARMv8 HeliX 1 at up to 2.4 GHz 2 or 4 ARMv8 HeliX 2 at up to 2.0 GHz
L1 Cache 32 KB I / 32 KB D per core (write-through with parity protection)
L2 Cache 256 KB shared per core pair (with ECC) 64
L3 Cache 4 or 8 MB shared 2 MB shared
DRAM 2x DDR3 Controllers with ECC (72b each) 1x DDR3 Controller with ECC (72b)
On-Chip Memory 1 MB 256 KB
Memory Bus Width 256-bit 256-bit
Low Power Features N/A < 250 mW standby
Coprocessors 4x Cortex-A5 at 500 MHz N/A
High-Speed Interfaces 2x 10G + 4x 1G + 1x 1G Management Ethernet 1x 10G + 4x 1G Ethernet
17x PCIe 3.0 (2 x8 + 1 x1 OR 1 x8 + 2 x4 + 1 x1 OR 4 x4 + 1 x1) 3x PCIe 3.0 (2 x1 OR 1 x4)
1 2x USB 3.0 Host 2x USB 3.0 Host + 1x USB 3.0 Host/Device
6x SATA III (four muxed with 4x 1G Ethernet) 1x SATA III

Applied Micro Helix 2 Block Diagram

The HeliX SoCs are sampling right now and slated to go into volume production in 2015. Applied Micro claims that design wins are already in place. From ARM's perspective, one can say that the juggernaut rolls on. With Cavium's Project Thunder and Broadcom's Vulcan targeting the high-end enterprise and datacenter segment, ARM needed an entry in the mid- to high-end embedded space currently dominated by MIPS64 and x86-64. The Applied Micro HeliX family brings ARM forward as a credible competitor for those sockets.

Source: Applied Micro

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  • TadzioPazur - Tuesday, October 14, 2014 - link

    Write-through L1 D cache, that's gonna hurt. Unless it has either high memory parallelism/load-store OOO, or hyperthreading of a sort (which it does not). This gets me thinking which segments this product is for, as low-performance cores with ECC memory (is it mandatory?) do not match up in my book. Probably frontend (webpage generation), cheap cloud nodes (if this things has required features, like memort/IO virtualization) or storage servers (someone already proposed this in the comments above).
    I guess we'll see when actual products are announced.
    Reply
  • Krysto - Friday, October 31, 2014 - link

    If APM wants to take the lead hard and fast, it should put Helix 3 on 16nm FinFET as soon as it can (hopefully early 2016 at most - late 2015 would be ideal). Reply

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