Intel's Xeon E5-2600 V2: 12-core Ivy Bridge EP for Servers
by Johan De Gelas on September 17, 2013 12:00 AM ESTJava Server Performance
The SPECjbb 2013 benchmark is based on a "usage model based on a world-wide supermarket company with an IT infrastructure that handles a mix of point-of-sale requests, online purchases and data-mining operations". It uses the latest Java 7 features and makes use of XML, compressed communication and messaging with security.
We tested with four groups of transaction injectors and backends. We applied a relatively basic tuning to mimic real world use.
"-server -Xmx4G -Xms4G -Xmn1G -XX:+AggressiveOpts -XX:+UseLargePages-server -Xmx4G -Xms4G -Xmn1G -XX:+AggressiveOpts -XX:+UseLargePages"
With these settings, the benchmark takes about 43GB of RAM. The first metric is basically maximum throughput.
The newest Xeon E5 2697 v2 delivers 33% better performance. The Opteron 6380 needs a 50% clock advantage to stay ahead of the 10-core Xeon E5. This illustrates how large the gap is between the Opterons and even the midrange Xeons. A 10-core Xeon E5-2660 V2 at 2.2GHz costs a bit more than the Opteron 6380 but will deliver a significantely better performance per watt, considering the very low 95W TDP.
The Critical-jOPS metric, is a throughput metric under response time constraint.
We have to admit we have our doubts. The Critical-jOPS measurements do not seem to be very repeateable and it is not completely clear how it is calculated. However, it confirms earlier measurements of our own that the Xeons are better at responding quickly at a given throughput. Again, the new Xeon 2697 v2 performs about 30% better than the Xeon E5 2690.
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Kevin G - Tuesday, September 17, 2013 - link
I'd be careful about using Java benchmarks on those SPARC chips for an overall comparison. The results on the SPARC side are often broken.x86 for many years has been ahead of SPARC. Only with the most recent chips has Oracle produced a very performance competitive chip.
The only other architecture that out runs Intel's best x86 chips is the POWER7/POWER7+. When the POWER8 ships, it is expected to be faster still.
Brutalizer - Thursday, September 19, 2013 - link
@Kevin G"...The results on the SPARC side are often broken..."
What do you mean with that? The Oracle benchmarks are official and anyone can see how they did it. Regarding the SPARC T5 performance, it is very fast, typically more than twice as fast as Xeon cpus. Just look at the official, accepted benchmarks on the site I linked to.
Kevin G - Friday, September 20, 2013 - link
@BrutalizerThere is a SPEC subtest whose result on SPARC is radically higher than other platforms. The weight of this one test affects the overall score. It has been a few years since I read up about this and SPARC as a platform has genuinely become performance competitive again.
Phil_Oracle - Friday, February 21, 2014 - link
Are you talking about libquantum?http://www.spec.org/cpu2006/Docs/462.libquantum.ht...
I believe IBM is the worst culprit on this subtest, showing a significant difference between base and peak. More so than any other vendor.
http://www.spec.org/cpu2006/results/res2012q4/cpu2...
But today, I believe all vendors have figured out how to improvise (cheat) on this test, even Xeon based.
http://www.spec.org/cpu2006/results/res2014q1/cpu2...
That’s why I believe SPEC CPU2006 is outdated and needs replacing and suggest looking at more realistic, recent (dal world) benchmarks like SPECjbb2013, SPECjEnterprise2010 or even TPC-H.
Phil_Oracle - Friday, February 21, 2014 - link
x86 was clearly ahead of SPARC till about SPARC T4 timeframe when Oracle took over R&D on SPARC. SPARC T4 allowed Oracle to equalize the playing field, especially in areas like database where the SPARC T4 really shines and shows considering many of the world record benchmarks that where released. When SPARC T5 came out last year, it increased performance by 2.4x, clobbering practically every other CPU out there. Today, you'll be hard pressed to find a real world benchmark, ones that are fully audited, where SPARC T5 is not in a leadership position, whether java based like SPECjbb2013 or SPECjEnterprise2010 or database like TPC-C or TPC-H.psyq321 - Tuesday, September 17, 2013 - link
I know that EX will be using the (scalable) memory buffer, which is probably the main reason for the separate pin-out. I guess they could still keep both memory controllers in, and fuse the appropriate one depending if it is an EX or EP SKU, if this would still make sense from a production perspective.Kevin G - Tuesday, September 17, 2013 - link
It wouldn't make much sense as the EX line up moves the DDR3 physical interface off to the buffer chip. There is a good chunk of die space used for the 256 bit wide memory interface in the EP line. Going the serial route, the EX line is essentially doubling the memory bandwidth while using the same number of IO pins (though at the cost of latency).The number of PCIe lanes and QPI links also changes between the EP and EX line up. The EP has 40 PCIe lanes where as the EX has 32. There are 4 QPI links on the EX line up making them ideal for 4 and 8 socket systems were as the EP line has 2 QPI links good for dual or a poor quad socket configuration.
psyq321 - Wednesday, September 18, 2013 - link
Hmm, this source: http://www.3dcenter.org/news/intel-stellt-ivy-brid...Claims that HCC is 12-15 core design. They also have a die-shot of a 15 core variant.
Kevin G - Thursday, September 19, 2013 - link
I'll 1-up you: Intel technical reference manuals (PDF).http://www.intel.de/content/dam/www/public/us/en/d...
http://www.intel.de/content/dam/www/public/us/en/d...
It does appear to be 15 core judging from the mask in the CSR_DESIRED_CORES register.
However, there is not indication that the die supports serial memory links to a buffer chip or >3 QPI links that an EX chip would have.
psyq321 - Thursday, September 19, 2013 - link
Well, I guess without Intel openly saying or somebody laser-cutting the die it would not be possible to know exactly is it a shared die between HCC EP and EX.However, there are lots of "hints" that the B-package Ivy Bridge EP hide more cores, like the ones you linked. If it is the case, it is really a shame that Intel did not enable all cores in the EP line. There would still be lots of places for differentiation between the EX and EP lines, since EX anyway contains RAS features without which the target enterprise customers would probably not even consider EP, even if it had the same number of cores.
Also, Ivy EX will have some really high TDP parts.