Socket-AM2+, Not So Positive?

When AMD first started talking about Phenom it boasted backwards compatibility with current Socket-AM2 motherboards, as well as a new Socket-AM2+ platform that would enable higher performance and better power management.

We are currently looking into Socket-AM2 motherboard compatibility, but not all vendors have Phenom-ready code for their motherboards as of today. While Phenom should work in virtually all Socket-AM2 motherboards, it's tough to say which will work by the time you can actually buy these things.


AMD's Spider platform, well, minus the graphics card - the 8800 GTX is still our testbed GPU of choice.

Socket-AM2+ motherboards, most of which are based on AMD's new 790FX chipset, were supposed to bring a tangible performance increase when paired with a Phenom processor. Phenom's L3 cache and North Bridge work on the same power plane, one separate from the rest of the CPU. Socket-AM2+ enables the use of two separate voltages, one for the L3 cache/NB and one for the rest of the CPU, whereas Socket-AM2 motherboards run the entire chip at the same voltage. The original plan was for Socket-AM2+ motherboards to run the L3 cache/NB at a higher frequency than the rest of the chip, unfortunately it looks like AMD wasn't able to make that happen.


Socket-AM2+ in action

Currently, the L3 cache/NB on these chips runs at a fixed frequency that's actually lower than the rest of the CPU frequency: 2.0GHz. We tested Phenoms running from 2.2GHz all the way up to 2.6GHz, and in all cases the L3 cache and North Bridge ran at 2.0GHz. We're not sure if this will ever get fixed, but it's somewhat disappointing as it was supposed to be a major reason for upgrading to Socket-AM2+ (but it's good news for current AM2 owners).

Right now it looks like the only benefit to Socket-AM2+ is support for DDR2-1066, which we've been having problems with internally already. If you've got a good Socket-AM2 motherboard, you may not need to upgrade to get the most out of Phenom.

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  • Proteusza - Monday, November 19, 2007 - link

    Actually, there is every possibility that he is right.

    First off, how much do you know about instruction sets and compilers? I'm going to assume nothing. If you do know something, then consider this for the edification of other readers.

    Compilers take code written in one language and produce an output in another. Specifically, compilers take code written in a language that can be easily understood by humans (ie C++) and output code that a machine can understand (machine code, or bytecode in the case of a JVM).

    Now, the problem with enhanced instruction sets, like SSE4, and SSE4.1 and SSE4a, is that they require compiler support. Imagine an instruction set as a vocabulary. And compilers are the programs that produce books, using a specified vocabulary. Now, the simple truth is that Intel makes extra effort to get its vocabulary into use. Thus, Cinebench was most likely compiled with Intel's latest vocabulary, and not AMD's.

    So, part of the K10 update was that it allowed SSE operations to be completed much faster, and I'm presuming this requires the use of its new instruction set. If so, that means that Cinebench was basically running in K8 mode.

    Not so far fetched, just means AMD has to make sure people update their code. The instruction set issue is another reason why RISC CPU's are generally simpler and faster.
  • JumpingJack - Monday, November 19, 2007 - link

    Look... it is code, that is all ... AMD and Intel are both designing to the same code base, run it on one... then run it on the other... which is faster?

    Architectural jargon of IMC and victim L3 cache, and x-bit look up ... if it doesn't work it doesn't work.
  • Kiijibari - Monday, November 19, 2007 - link

    Lol .. just code ... imagine a guy talking in a south west Chinese dialect to you. You do not understand anything ? Well .. it is just a language ... ;-)

    No offense intended: Please do some read up on compliers and programming languages .. it is interesting :)

    cheers

    Kiiji
  • Brunnis - Monday, November 19, 2007 - link

    Acutally, there shouldn't be any code modifications needed to make use of the new SSE functionality. The difference is internal to the CPU, meaning that it now processes SSE instructions without splitting them. The instructions used are the same as before.

    That said, there may be untapped potential in the CPU that can be uncovered by the use of a different compiler (due to other reasons). Though, as far as I know, Intel compilers often produce faster code even for AMD CPUs...

    About the "architectural advantage" Anand mentioned: Of course the Core 2 has an architectural advantage. It's pretty obvious from the fact that it performs faster, clock-for-clock, in almost all cases while having much higher frequency potential. Not even AMD's integrated memory controller can raise the computational efficiency of their CPU enough to really challenge Intel. AMD may have a more elegant external design and interface to the rest of the system (native quad, HyperTransport, integrated memory controller), but Intel obviously has the more refined internal design. Sadly for AMD, a computational advantage seems to weigh heavier than a neat system/core interface in this case.
  • Kiijibari - Monday, November 19, 2007 - link

    quote:

    Acutally, there shouldn't be any code modifications needed to make use of the new SSE functionality. The difference is internal to the CPU, meaning that it now processes SSE instructions without splitting them. The instructions used are the same as before.
    Yes I know what you mean, the SSE instructions are the same, they are just executed faster (in 1 clock compared to 2 clocks before). That is correct, however I wonder how much code is out there that is compiled with the old Intel compilers until 9.X.

    The problem with these compilers were, that they did not executed the SSE2 codepath on AMD chips, even if the CPU would have been capable of executing it. Instead a slower FPU code is used for AMD K8s.

    The newest Intel 10 Compilers have now new compiler flags that can generate SSE2 code for non-intel CPUs, however I did not have seen benches of these so far.

    Even the M$ Compiler had some nasty SSE disable "features":
    http://einstein.phys.uwm.edu/forum_thread.php?id=6...">http://einstein.phys.uwm.edu/forum_thread.php?id=6...

    All in all, I guess there are a lot of programs out there that disable SSE on AMD CPUs :( Therefore a plain compile test of several open-sorce prgorams with gcc / Sun / Pathscale compilers would be nice. Intel CPUs could be benched with Intel compiler, too, any CPU should gets it best code.

    cheers

    Kiiji
  • Kiijibari - Monday, November 19, 2007 - link

    Yet another wise guy knowing nothing ...

    Lets imagine an English native speaker ... would he understand Spanish ? No, not much ... but maybe his fried, who learned Spanish in school is better in speaking Spanish, nevertheless, he wont be as good as a native Spanish speaker ...

    Who would be the guy with the "superior, best language capabilities" now? The Spanish, the English speaking guy, or his friend ?

    Think about it a little bit I am curious about your reply ^^

    cheers

    Kiiji
  • MrKaz - Monday, November 19, 2007 - link

    “AMD couldn't simply get enough quantities of the Phenom at 2.4GHz to have a sizable launch this year (not to mention a late discovery of a TLB error in the chips),…”

    I’m very interested in the bug you talked Anand.
    Could you say if you know how it affects the CPU:
    -Performance?
    -Clock speed?
    -Slow northbridge clocks?
    Or the bug no longer exists in these CPUs?


    Complete disappointment.
    At least AMD release the 790 motherboards so I can at least put my old CPU on that system with two Ati 3850 cards… ;)
  • Spoelie - Monday, November 19, 2007 - link

    The bug freezes the system at high workloads. It shouldn't have any performance impact.

    I'm extremely disappointed with phenom, I was planning to get the entire spider platform for my yearly upgrade cycle, but that seems to be a bad idea.
  • fitten - Monday, November 19, 2007 - link

    quote:

    The bug freezes the system at high workloads. It shouldn't have any performance impact.


    I would think that transitioning from a running, working system into a brick (not running and not working) would be a fairly significant performance impact ;)
  • Viditor - Monday, November 19, 2007 - link

    quote:

    I'm extremely disappointed with phenom, I was planning to get the entire spider platform for my yearly upgrade cycle, but that seems to be a bad idea


    I'm waiting for the review on Quad-Crossfire first...
    I figure I can get 4 x 3850s for about the same price as an 8800 Ultra. The question is, is it worth it?
    If XfireX is good, then I will pull the trigger on 4 x 3850s (or 3870s if I can get them before Xmas), a 790FX mobo, and probably a Phenom 9500...
    Then I'll upgrade the Phenom in March when the B3s finally come out.

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