Even More Tweaks

Translation Lookaside Buffers, TLBs for short, are used to cache what virtual addresses map to physical memory locations in a system. TLB hit rates are usually quite high but as programs get larger and more robust with their memory footprint, microprocessor designers generally have to tinker with TLB sizes to accommodate. With K8 AMD increased the size of its TLBs over K7, and with Barcelona AMD is repeating the process once more.

Barcelona's TLBs are slightly larger than K8's, but they now include support for 1G pages which are useful for database applications and virtualized workloads. AMD also introduced a 128 entry 2M L2 TLB with Barcelona, once again to help cope with newer programs using larger page sizes. The TLB improvements to Barcelona won't make any sort of tangible impact on desktop applications, but enterprise performance should improve in server applications with large memory footprints.

When Intel introduced its second Pentium M, codenamed Dothan, one of the enhancements made was a lower integer divide latency. Although details at the time are slim, AMD has indicated that it has moved to reduce integer divide latency in Barcelona as well. We're not sure if the changes implemented are similar in any way to what Intel did with Dothan, but don't expect the performance improvement to be vastly noticeable in real world applications. It's one of those tweaks that will add up to overall more efficient execution but not one that's going to give you double digit performance gains across the board.

In another attempt to effectively "widen" Barcelona without committing a significant amount of transistors to doing so, AMD took a couple of instructions that were microcoded and turned them into fastpath decode instructions. A microcoded instruction takes significantly longer to decode than an instruction able to go through one of the core's fastpath decoders. CALL and RET-Imm instructions are now fastpath, which is a part of Barcelona's sideband stack optimization enhancements. MOVs from SSE registers to integer registers are now fastpath as well.

While on the topic of instructions, AMD also introduced a few new extensions to its ISA with Barcelona. There are two new bit manipulation instructions: LZCNT and POPCNT. Leading Zero Count (LZCNT) counts the number of leading zeros in an op, while Pop Count counts the leading 1s in an op. Both of these instructions are targeted at cryptography applications.

AMD also introduced four new SSE extensions: EXTRQ/INSERTQ, MOVNTSD/MOVNTSS. The first two extensions are mask and shift operations combined into a single instruction, while the latter two are scalar streaming stores (streaming stores that can be done on scalar operands). We may see some of these same instructions included in Penryn and other future Intel processors.

Stacks and Loads of Optimizations A Faster Memory Controller
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  • johnsonx - Saturday, March 03, 2007 - link

    Actually that's the new Double-Dog-Dare RAM-3.
    Reply
  • JarredWalton - Thursday, March 01, 2007 - link

    Crazy D's... they're like rabbits! Reply
  • AkumaX - Thursday, March 01, 2007 - link

    Great read. I love Anand's articles. We'll see what the future holds, for both AMD and Intel Reply
  • MAME - Thursday, March 01, 2007 - link

    I wonder how much market share AMD will lose until this chip become readily available. Reply
  • tuteja1986 - Thursday, March 01, 2007 - link

    None... AMD will loose no marketshare. They are in bloody price war... Intel hasn't really regained any lost territory. But Intel have the advantage of performance is trying to find a breakthrough in AMD market share to retake back the lost territory. AMD is still selling everything they make but at huge looses caused by the price war.
    Reply
  • Griswold - Thursday, March 01, 2007 - link

    Huge loses? Do you mistake the loss of Q406 due to the ATI purchase as a loss due to selling under production costs? Reply
  • Phynaz - Thursday, March 01, 2007 - link

    Seen that AMD cach flow recently? Reply
  • TwistyKat - Thursday, March 01, 2007 - link

    ...you have people like me who won't buy anything from Intel. If we didn't have AMD to make Intel competitive we would never have the range of choices we have today. We'd all be running monster Itanics with massive electricity bills.

    Intel has the resources to effectively put AMD out of business over time if it so chooses, and today I suspect they are focused on something close to that.


    Reply
  • fitten - Thursday, March 01, 2007 - link

    quote:

    Intel has the resources to effectively put AMD out of business over time if it so chooses, and today I suspect they are focused on something close to that.


    Won't happen. In order to avoid anti-trust lawsuits, Intel will give AMD money to keep them afloat before they'll allow AMD to fail.
    Reply
  • GoatMonkey - Friday, March 02, 2007 - link

    If AMD were to be purchased by a larger corporation, like IBM, it would leave Intel free to beat AMD down with all of their resources. Of course, at that point AMD would have the resources of IBM behind it and could potentially fight back better. Reply

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