Sideband Stack Optimizer

Intel's very first Pentium M introduced a feature Intel called its dedicated stack manager. As its name implies, the dedicated stack manager was used to handle all x86 stack operations (i.e. push, pop, call, return). The purpose of the stack manager was to keep those stack operations, which are frequently used with function calls in code, separate from the rest of the x86 instruction stream sent to the CPU. The dedicated stack manager would handle decode and "execution" of these operations so that they wouldn't clog up the processor's decoders and execution units later in the pipeline. Intel essentially "widened" the core by offloading some operations to separate hardware.

With Barcelona, AMD is introducing a similar technology it is calling a Sideband Stack Optimizer. Stack instructions no longer go through the 3-way decoder and stack operations no longer go through the integer execution units, effectively widening Barcelona at minimal cost. The Sideband Stack Optimizer, like Intel's dedicated stack manager, features its own adder that handles all stack operations. It's a small tweak that can help overall performance, and it's simply one that made sense for AMD to implement.

Faster Loads

When looking at the performance of the Athlon 64 and Intel's Core 2 processors, it's easy to understand why Intel has a strong performance advantage in applications that make heavy use of SSE. But what about applications like gaming and business apps that should greatly benefit from AMD's on-die memory controller? Is the Core 2's larger L2 cache and aggressive prefetchers all that it needs to overcome AMD's on-die memory controller?

One major aspect of Intel's Core micro-architecture advantage is its ability to allow load instructions to bypass previous load and store instructions. On average, about 1/3 of all instructions in a program end up being loads, thus if you can improve load performance you can generally impact overall application performance pretty significantly. With Intel's Core micro-architecture, it's possible for loads to be re-ordered to ensure that instructions dependent on those loads get the data they need without waiting for costly memory accesses.

Core also allowed for loads to be moved ahead of stores, which was previously not allowed due to the possibility that an earlier store could invalidate the data that was just loaded. Intel figured that the possibility of a store writing over a load ends up being very small, on the order of 1 - 2%, therefore with a reasonably accurate predictor you could correctly guess when re-ordering a load ahead of a store was possible. Intel's Core 2 based processors feature prediction logic to guess whether a store and a load share the same memory address; if the predictor determines that they won't, then it allows the load to be re-ordered ahead of the store. In the small chance that the predictor is incorrect however, the load has to be redone at the cost of a pipeline flush (similar to what happens if the processor mispredicts a branch).

AMD's K8 architecture had no equivalent scheme for allowing the out of order execution of loads ahead of other loads and stores, so even without an on-die memory controller Intel was able to execute some memory operations faster than AMD. Barcelona fixes this problem through an almost identical scheme to what Intel implemented in its Core 2 processors.

Barcelona can now re-order loads ahead of other loads, just like Core 2 can. It can also execute loads ahead of other stores, assuming that the processor knows that the two don't share the same memory address. While Intel uses a predictor to determine whether or not the store aliases with the load, AMD takes a more conservative approach. Barcelona waits until the store address is calculated before determining whether or not the load can be processed ahead of it. By doing it this way, Barcelona is never wrong and there's no chance of a mispredict penalty. AMD's designers looked at using a predictor like Intel did but found that it offered no performance improvement on its architecture. AMD can generate up to three store addresses per clock as it has three AGUs (Address Generation Units) compared to Intel's one for stores, so it would make sense that AMD has a bit more execution power to calculate a store address before moving a load ahead of it.

The out of order load execution improvements to Barcelona should prove to be even more effective than they were in Core 2 given that AMD previously couldn't do any reordering of loads before the Int/FP schedulers whereas Core Duo could do a limited amount of re-ordering.

Core Tune-up Even More Tweaks
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  • Amiteriver - Tuesday, March 27, 2007 - link

    Sounds groooovy
    Now lets just hope they have something good to plug it into.
    Reply
  • trisweb2 - Friday, March 16, 2007 - link

    I just want to say how refreshing it is to read an article written by Anand. He is a master of the English language; he perfectly communicates and explains every technical detail and I come away with a better understanding of whatever he's talking about.

    Thank you, Anand, for being a good writer!
    Reply
  • MrWizard6600 - Thursday, March 22, 2007 - link

    I Agree, Outstanding.

    No other site I know of gives nearly as many in depth details, and while ill admit my knowlage of some of the terms is sketchy, I got through that one with a good understanding.

    Sounds like AMD has something to fight Core 2 against.

    I do have one criticism:
    I would have loved to have heard what Intels equivilent to all of AMDs technologies would be, mind you this criticism corrects it self toward the end of the artical.
    Reply
  • stance - Monday, March 05, 2007 - link

    Remember AMD's old president and CEO Jerry Sanders with comments
    like "We will see what we see" and "More bang for your buck" I
    cannot wait to see duel socket motherboards with two four core
    Barcelona's working their magic. reminds me of Carol shelby
    when he brought the Cobra out for road test. exciting is not
    the word, jaw droping performance? Don't take Richard's Statements
    lightly
    Reply
  • lordsnow - Sunday, March 04, 2007 - link

    Does anyone have any idea how compatible the "Barcelona" CPU will be with current motherboards? When it comes out, does it need a new n-phase voltage regulator, for example?

    the reason I'm asking is, I want to upgrade and with the current state of affairs was going to go for a C2D CPU. But with these Barcelona CPU's due out I may stick with AMD - get a AM2 motherboard and cheap AM2 CPU and upgrade to the Barcelona CPU at a later date. But I have to be sure that whatever motherboard I buy now will be 100% Barcelona compatible.

    Can anyone inform us about what the situation is in this regard?
    Reply
  • coldpower27 - Sunday, March 04, 2007 - link

    Barcelona being the server variant will be compatible with the Socket F infrastructure, while Agena will be a Socket AM2+ processor compatible with exisiting Socket AM2 infrastructure.

    Reply
  • lordsnow - Sunday, March 04, 2007 - link

    Any ideas as to what kind of features a user will be missing by dropping a AM2+ "Agena" CPU into a AM2 socket? The enhanced Power Saving features, perhaps?
    Reply
  • chucky2 - Sunday, March 04, 2007 - link

    I asked above and non-AnandTech folks like you and I said it would...but no one from AnandTech themselves jumped right in to give an affirmative.

    I asked for links from AMD's own website confirming that Agena and Kuma would work in current AM2 motherboards, and no one posted back.

    Right now the AM2+ CPU's will work in current AM2 boards rumor is just that, a rumor...when AMD themselves confirm it, or a site such as AnandTech confirms it with AMD and reports on it, then I'll believe it.

    Until then, it's <i>probable</i> that AM2+ will work in current AM2 motherboards...if you're willing to take the risk I say go for it, else, wait until we have an official answer one way or the other.

    JMHO...

    Chuck
    Reply
  • Calin - Saturday, March 03, 2007 - link

    "Intel regained the undisputed performance crown it hadn't seen ever since the debut of AMD's Athlon 64."
    Intel in fact lost the "undisputed performance king" title during the early lifetime of the K7 architecture. The Pentium !!! was faster at some tasks and slower at others (games) than the K7. Before that, the Pentium II was better than the K6-2 (the K6-3 had better IPC than Pentium3, but was slower in MHz)
    Reply
  • coldpower27 - Sunday, March 04, 2007 - link

    Intel had the undisputed performance crown again with the Athlon XP 3200+ vs the Pentium 4 3.0C/3.2C and higher processors. Reply

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