AM5 Chipsets: X670 and B650, Built by ASMedia

Finally, let’s talk about the chipsets that are going to be driving the new AM5 platform. Kicking things off, we have the B650 and X670 chipsets, as well as their Extreme variations. Since AMD is starting the rollout of their new platform with their high-end CPUs, they are matching this with the rollout of their high-end chipsets.

For this week’s launch, the initial boards available are all from the X670 family. B650 boards will, in turn, be coming next month. We’ll break down the difference between the two families below, but at a high level, X670 offers more I/O options than B650. And while not strictly a feature of the chipset, the market segmentation is such that the bulk of high-end AM5 boards – those boards with a massive amount of VRMs and other overclocker/tweaker-friendly features – will be X670 boards.

That said, for simplicity’s sake we’re going to start with the B650 chipset, and build up from there.

AMD AM5 Chipset Comparison
Feature X670E X670 B650E B650
CPU PCIe (PCIe) 5.0 (Essentially Mandatory) 4.0
(5.0 Optional)
5.0 (Essentially Mandatory) 4.0
(5.0 Optional)
CPU PCIe (M.2 Slots) At Least 1 PCIe 5.0 Slot
Total CPU PCIe Lanes 24
Max Chipset PCIe Lanes 12x 4.0 + 8x 3.0 8x 4.0 + 4x 3.0
SuperSpeed 10Gbps USB Ports 4 CPU + 12 Chipset
or
4 CPU + 10 Chipset + 1 Chipset 20Gbps
or
4 CPU + 8 Chipset + 2 Chipset 20Gbps

4 CPU + 6 Chipset
or
4 CPU + 4 Chipset + 1 Chipset 20Gbps

DDR5 Support Quad Channel (128-bit bus)
Speeds TBD
Wi-Fi 6E Yes
CPU Overclocking Support Y Y Y Y
Memory Overclocking Support Y Y Y Y
Available September 2022 October 2022

B650, AMD’s mainstream AM5 chipset, can best be thought of as a PCIe 4.0 switch with a bunch of additional I/O baked in. And as is typical for chipsets these days, several of the I/O lanes coming from the chipset are flexible lanes that can be reallocated between various protocols. Meanwhile, uplink to the CPU is a PCIe 4.0 x4 connection.

For PCIe connectivity, B650 offers 8 PCIe 4.0 lanes, which can either have PCIe slots or further integrated peripherals (LAN, Wi-Fi, etc) hung off of them. This and the uplink speed are both notable improvements over the B550 chipset, which was PCIe 3.0 throughout, despite Ryzen 3000/5000 offering PCIe 4.0 connectivity. So B650 has a lot more bandwidth coming into it, and available to distribute to peripherals.

There are also a quartet of PCIe 3.0 lanes which are shared with the SATA ports, allowing for either 4 PCIe lanes, 2 lanes + 2 SATA, or 4 SATA ports. Notably, the dedicated SATA ports found on the 500 series chipsets are gone, so motherboards will always have to sacrifice PCIe lanes to enable SATA ports. For the B650 this amounts to a net loss of 2 SATA ports, as the most ports it can drive without a discrete storage controller is 4.

Meanwhile on the USB front, motherboard vendors get more Superspeed USB ports than before. The chipset offers a fixed 4 10Gbps Superspeed ports, and then an additional output can be configured as either a single 20Gbps (2x2) port, or two 10Gbps ports. Finally, the chipset can drive a further 6 USB 2 ports, mostly for on-board peripheral use. There are no USB root ports limited to 5Gbps here, so all USB 3.x ports, whether coming from the CPU or the chipset, are capable of 10Gbps operation.

AMD has once again outsourced chipset development for this generation to ASMedia, who also designed the B550 chipset. AMD has not disclosed a TDP for the chipset, but like B550 before it, it is designed to run with passive cooling.

Outside of the technical capabilities of the B650 chipset itself, AMD is also imposing some feature requirements on motherboard makers as part of the overall AM5 platform, and this is where the Extreme designation comes in. All B650 (and X670) motherboards must support at least 1 PCIe 5.0 x4 connection for storage; Raphael has enough lanes to drive two storage devices at those speeds, but it will be up to motherboard manufacturers if they want to actually run at those speeds (given the difficulty of PCIe 5.0 routing).

Extreme motherboards, in turn, will also require that PCIe 5.0 is supported to at least one PCIe slot – normally, the x16 PCIe Graphics (PEG) slot. Non-extreme motherboards will not require this, and while motherboard vendors could technically do it anyhow, it would defeat the purpose of (and higher margins afforded by) the Extreme branding. Conversely, while AMD has been careful to toe a line about calling 5.0 slots outright mandatory on Extreme motherboards, it’s clear that there’s some kind of licensing or validation program in place where motherboard makers would be driving up their costs for no good reason if they tried to make an Extreme board without 5.0 slots.

It’s frankly more confusing than it should be, owing to a lack of hard and definite rules set by AMD; but the messaging from AMD is that it shouldn’t be a real issue, and that if you see an Extreme motherboard, it will offer PCIe 5.0 to its graphics slot. Past that, offering 5.0 to additional slots, bifurcation support, etc is up to motherboard vendors. The more PCIe 5.0 slots they enable, the more expensive boards are going to be.

Meanwhile the high-end counterpart to the B650 chipset is the X670 chipset, which is pretty much just two B650 chipsets on a single board. While not explicitly confirmed by AMD, as we’ll see in the logical diagram for X670, there’s no way to escape the conclusion that X670 is just using B650 dies daisy chained off of one another to add more I/O lanes.

Officially, X670 is a two-chip solution, using what AMD terms the “downstream” and “upstream” chipsets. The upstream chip is connected to the CPU via a PCIe 4.0 x4 connection, and meanwhile the downstream chip is connected to the upstream chip via another PCIe 4.0 x4 connection.

By doubling up on the number of chips on board, the number of I/O lanes and options are virtually doubled. The sum total of the two chips offers up to 12 PCIe 4.0 lanes (the last 4 are consumed by the upstream chip feeding the downstream chip) and a further 8 PCIe 3.0 lanes that can be shifted between PCIe and up to 8 SATA ports.

Meanwhile on the USB front, there are now 8 fixed USB 2 ports and 8 fixed SuperSpeed USB 10Gbps ports. For USB flex I/O, motherboard makers can select from either 2 20Gbps ports, 1 20Gbps port plus 2 10Gbps ports, or 4 10Gbps ports.

And while this configuration adds more I/O lanes (and thus more I/O bandwidth), it should be noted that all of these I/O lanes are still gated behind the PCIe 4.0 x4 connection going back to the CPU. So the amount of backhaul bandwidth available between the chipsets and the CPU is not any higher than it is on B650. The name of the game here is flexibility; AMD is not designing this platform for lots of sustained, high-speed I/O outside of the CPU-connected x16 PCIe graphics slot and M.2 slots. Rather, it’s designed to have a lot of peripherals attached that are either low bandwidth, or only periodically need high bandwidths. If you need significantly more sustained I/O bandwidth, then in AMD’s ecosystem there is a very clear push towards Threadripper Pro products.

Finally, X670 Extreme (X670E) will impose the same PCIe 5.0 requirements as B650E. This means Extreme boards will offer PCIe 5.0 connectivity for at least one PCIe lane, while X670 boards are expected to come with just PCIe 4.0 slots. These will be the most expensive boards, owing to a combination of requiring two chipsets, as well as the extra costs and redrivers that go into extending PCIe 5.0 farther throughout a motherboard.

On that note, when discussing the new chipsets with AMD, the company did offer an explanation for why X670 daisy chains the chipsets. In short, daisy chaining allows for additional routing – the downstream chipset can be placed relative to the upstream chipset, instead of relative to the CPU (and PCIe devices then placed relative to the chipsets). In other words, this allows for spreading out I/O so that it’s not all so close to the CPU, making better use of the full (E)ATX board. As well, hanging both chipsets off of the CPU would consume another 4 PCIe lanes, which AMD would rather see going to additional storage.

More I/O For AM5: PCIe 5, Additional PCIe Lanes, & More Displays DDR5 & AMD EXPO Memory: Memory Overclocking, AMD's Way
POST A COMMENT

205 Comments

View All Comments

  • Oxford Guy - Tuesday, September 27, 2022 - link

    This has been posted for years. Reply
  • BoredInPDX - Tuesday, September 27, 2022 - link

    I’m confused. I they 720p tests you write:
    “All gaming tests here were run using integrated graphics, with a variation of 720p resolutions and at minimum settings.”

    Yet all the prior-gen AMD CPUs tested are lacking an IGP. Am I missing something?
    Reply
  • Ryan Smith - Friday, September 30, 2022 - link

    You are not missing anything; we did not run any iGPU tests. That's a bit of boilerplate text that did not get scrubbed from this article. Thanks for bringing it up! Reply
  • Gigaplex - Wednesday, September 28, 2022 - link

    There's some odd results here and the article commentary doesn't seem to touch on it. Why is the 7600X absolutely trounced in Geekbench 4.0 MT? The second slowest CPU (3600XT) more than doubles it. And yet the 7950X wins by a mile in that same test, so it shouldn't be architectural. And in some of the gaming tests, the 7600X wins, and in some it comes dead last. Reply
  • Dribble - Wednesday, September 28, 2022 - link

    The processors are particularly cache bound - i.e. it fits in cache it runs very fast, if it doesn't it falls off rapidly. That is often visible in games where it'll run amazingly in some (mostly older) games, but tend to fall off, particularly in the lows, in more complex (mostly newer) games. Reply
  • ricebunny - Wednesday, September 28, 2022 - link

    The SPEC multithreaded tests are N separate instantiations of the single thread tests. That’s a perfect scenario where there is no dependency or serialization in the workload and tells us very little how the CPUs would perform in a parallel workload application. There are SPEC tests specifically designed to test parallel performance, but I do not see them included in this report. Anandtech, can you comment on this? Reply
  • abufrejoval - Wednesday, September 28, 2022 - link

    Emerging dGPUs not supporting PCIe 5.0 is just crippleware!

    While I can easily see that 16 lanes of PCIe 5.0 won't do much for any game, I can very much see what I'd do with the 8 lanes left over when all dGPU bandwidth requirements can be met with just 8 lanes of PCIe 5.0.

    Why can't they just be good PCIe citizens and negotiate to use 16 lanes of PCIe 4.0 on lesser or previous generation boards and optimize lane allocation on higher end PCIe 5.0 systems that can then use bifurcation to add say a 100Gbit NIC, plenty of Thunderbolt 4 or better yet, something CXL?

    Actually I'd be really astonished if this wasn't even an artifical cap and that the Nvidia chips may actually be able to do PCIe 5.0.

    It's just that they'd much rather have people use NVlink.
    Reply
  • TheinsanegamerN - Tuesday, October 4, 2022 - link

    Um....dude, 4.0x16 and 5.0x8 have the same bandwidth, and no GPU today can saturate 4.0, not even close. The 300ti OCed manages to saturate.....2.0. 3.0 is a whopping 7% faster.

    You got awhile man.
    Reply
  • abufrejoval - Wednesday, September 28, 2022 - link

    It should be interesting to see if AMD is opening the architecture for 3rd parties to exploit the actual potential of the Ryzen 7000 chips.

    The current mainboard/slot era that dates back to the 1981 IBM-PC (or the Apple ][) really is coming to an end and perhaps few things highlight this as well as a 600 Watt GPU that has a 65 Watt mainboard hanging under it.

    We may really need something more S100 or VME, for those old enough to understand that.

    Thunderbolt cables handle 4 lanes of PCIe 3.0 today and AFAIK cables are used for much higher lane counts and PCIe revisions within high-end server chassis today, even if perhaps at shorter lengths and with connectors designed for somewhat less (especially less frequent) pluggability.

    Their main advantage is vastly reduced issues with mainboard traces and much better use of 3D space to optimize air flow cooling.

    Sure those cables aren't cheap, but perhaps the cross-over point for additional PCB layers has been passed. And optical interconnects are waiting in the wings: they will use cables, too.

    You stick PCIe 5.0 x4 fixed length cables out from all sides of an AM5 socket and connect those either to high bandwidth devices (e.g. dGPU) or a switch (PCIe 5.0 variant of the current ASMedia), you get tons of flexibility and expandability in a box form factor, that may not resemble an age old PC very much, but deliver tons of performance and expandability in a deskside form factor.

    You want to recycle all your nice PCIe 3.0 2TB NVMe drives? Just add a board that puts a PCIe 5.0 20 lane switch between (even PCIe 4.0 might do fine if it's 50% $$$).

    And if your dGPU actually needs 8 lanes of PCIe 5.0 to deliver top performance, connect two of those x4 cables to undo a bit of bifurcation!

    How those cable connected board would then mount in a chassis and be cooled across a large range of form factors and power ranges is up for lots of great engineers to solve, while dense servers may already provide lots of the design bricks.

    Unfortunately all that would require AMD to open up the base initialization code and large parts of the BIOS, which I guess currently has the ASmedia chip(s) pretty much hardwired into it.

    And AMD with all their "we don't do artificial market segmentation" publicity in the past, seem to have become far more receptive to its bottom line benefits recently, to allow a free transition from console to PC/workstation and servers of all sizes.

    And it would take a high-volume vendor (or AMD itself), a client side Open Compute project or similar to push that form factor the the scale where it becomes economically viable.

    It's high time for a PC 2.0 (which isn't a PS/2) to bridge into the CXL universe even on desktops and workstations.
    Reply
  • Oxford Guy - Wednesday, September 28, 2022 - link

    "The current mainboard/slot era that dates back to the 1981 IBM-PC (or the Apple ][)"

    Absolutely nothing about the IBM PC was new. The Micral N introduced slots in a microcomputer and the S-100 bus, introduced by the Altair, became the first big standard.
    Reply

Log in

Don't have an account? Sign up now