AMD Zen 4 Ryzen 9 7950X and Ryzen 5 7600X Review: Retaking The High-End
by Ryan Smith & Gavin Bonshor on September 26, 2022 9:00 AM ESTMore I/O For AM5: PCIe 5, Additional PCIe Lanes, & More Displays
AMD’s other big expenditure using socket AM5’s additional pins is on I/O support. While AM4 already supported a fair bit of I/O, including 24 PCIe lanes, 3 displays, and 4 Superspeed USB ports, there was still room for improvement. So for AM5, AMD has increased the amount of I/O and the flexibility offered with the platform.
The biggest change here is that the AM5 socket now provides for 28 lanes of PCIe, a net gain of 4 lanes. More significantly still, PCIe 5.0 is now supported (at least on the Ryzen 7000 “Raphael” processors), doubling the bandwidth of all of those PCIe lanes to a max of 4GB/sec/lane. Which gives the chip a maximum cumulative PCIe bandwidth of 112GB/sec in each direction.
In practice, those additional lanes are intended for NVMe drives, giving AM5 a second x4 connection to drive a second NVMe drive; though we have seen some motherboard designs where vendors are stealing the second x4 for a PCIe 5.0 x4 slot. Past that, things look a lot like AM4, with 16 PCIe lanes to directly drive one or more PCIe slots, and then 4 lanes for hooking up the chipset.
Meanwhile, the updated socket also offers enough pins for the CPU to drive 4 Superspeed USB 3.x ports, and a USB 2 port. The USB 2 port is new for this generation, and meanwhile 3 of those USB 3 ports now also support the USB Type-C connector, unlike AM4 which could only natively drive Type-A ports. As a result, AM5 CPUs can drive a total of 3 Superspeed Type-C ports, a fourth Superspeed Type-A port, and then the aforementioned USB 2 port.
There has been one regression, however, and that is SATA support. Whereas AM4 CPUs could drive a mix of NVMe and SATA drives (up to 2 SATA + a PCIe x2 for NVMe), AM5 is purely PCIe. So there is no native SATA support on the CPU, and supplying that will come from the chipset.
To visualize this, we’ll use part of the AM5 chipset diagram. We’ll go more into the specifics of the chipsets in a bit, but lays out what is wired to the CPU, and what will need to be wired to the chipset. Of note there, the current chipsets only use PCIe 4.0 connectivity to the Ryzen CPU, so the current generation of chipsets will not be making full use of the bandwidth capabilities of the CPU itself.
Which with the addition of PCIe 5.0 support to the platform, is going to be a recurring theme. While AMD has baked in 5.0 support into the Raphael CPUs, it’s up to motherboard vendors to actually make it so. Compared to PCIe 4.0, 5.0 has much tighter signal integrity requirements (the signaling frequency has been doubled), which at least at this time, makes PCIe 5.0 expensive to implement. A very well-designed motherboard is required with impeccable traces, and on top of that the overall short throw of PCIe 5.0 means that retimers/redrivers become necessary rather quickly. So while AM5 can support PCIe 5.0 throughout, the reality is that we’re still going to see a lot of PCIe 4.0 in use even in higher-end motherboards.
As for the necessity of PCIe 5.0 overall, thus far AMD is primarily focused on what it means for NVMe drive speeds. The first generation of PCIe 5.0-enabled consumer SSDs are expected to land a bit later this year, and they should be able to hit sequential burst transfer rates above the limits of PCIe 4.0 (~7GB/sec).
Past that, NVIDIA’s newly announced Ada Lovelace architecture GeForce RTX 40 series video cards do not support PCIe 5.0. So while we’re awaiting AMD to announce their RDNA 3-based product lineup later this year, regardless of what AMD does, the bulk of video cards sold next year are not going to use PCIe 5.0. So there is a bit less pressure on motherboard manufactures (and motherboard buyers) to get boards that support PCIe 5.0 to anything beyond a couple of M.2 slots.
Finally, in conjunction with the USB I/O changes, AM5 also introduces some display I/O changes. Whereas AM4 could directly drive up to 3 displays, AM5 brings this to 4. Specifically, AM5 offers one dedicated display output (which will generally be allocated to HDMI), while the other 3 display outputs are available over those 3 USB Type-C ports as DisplayPort alt mode. It’ll be up to motherboard manufacturers if they want to expose any of these USB-C root ports as physical USB-C ports or as DisplayPorts, but so far from the motherboard designs we’ve seen, the former is more common (though certainly not universal).
Anticipating a shift to more USB Type-C displays, AMD is also implementing what they call “hybrid graphics” support on AM5. Unlike previous products where this referred to linking up the integrated graphics with a discrete GPU in CrossFire mode, this time around it refers to being able to being able to use the mobo/iGPU’s display outputs to drive a monitor while using a dGPU to render content. This is largely lifted from AMD’s laptop technologies, where similar techniques are used to allow the dGPU to be powered down when it’s not in use. In the case of desktop processors, this just means every display output will work, regardless of whether it’s plugged into ports coming from the CPU or a discrete video card.
It’s also worth noting that AM5 is bringing a few other, more minor updates to other comms protocols. Among these is support for MIPI’s (relatively) new I3C chip-to-chip signaling standard, which will ultimately be supplanting the long-used I2C standard. As well, AM5 doubles the number of I2C/I3C ports available, bringing the total to 4 ports. The platform also adds a second (enhanced) Serial Peripheral Interface (eSPI/SPI) port, and on the audio front, adds support for the Digital Mic and MIPI’s Soundwire standard for low-cost audio peripherals.
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Oxford Guy - Tuesday, September 27, 2022 - link
This has been posted for years. ReplyBoredInPDX - Tuesday, September 27, 2022 - link
I’m confused. I they 720p tests you write:“All gaming tests here were run using integrated graphics, with a variation of 720p resolutions and at minimum settings.”
Yet all the prior-gen AMD CPUs tested are lacking an IGP. Am I missing something? Reply
Ryan Smith - Friday, September 30, 2022 - link
You are not missing anything; we did not run any iGPU tests. That's a bit of boilerplate text that did not get scrubbed from this article. Thanks for bringing it up! ReplyGigaplex - Wednesday, September 28, 2022 - link
There's some odd results here and the article commentary doesn't seem to touch on it. Why is the 7600X absolutely trounced in Geekbench 4.0 MT? The second slowest CPU (3600XT) more than doubles it. And yet the 7950X wins by a mile in that same test, so it shouldn't be architectural. And in some of the gaming tests, the 7600X wins, and in some it comes dead last. ReplyDribble - Wednesday, September 28, 2022 - link
The processors are particularly cache bound - i.e. it fits in cache it runs very fast, if it doesn't it falls off rapidly. That is often visible in games where it'll run amazingly in some (mostly older) games, but tend to fall off, particularly in the lows, in more complex (mostly newer) games. Replyricebunny - Wednesday, September 28, 2022 - link
The SPEC multithreaded tests are N separate instantiations of the single thread tests. That’s a perfect scenario where there is no dependency or serialization in the workload and tells us very little how the CPUs would perform in a parallel workload application. There are SPEC tests specifically designed to test parallel performance, but I do not see them included in this report. Anandtech, can you comment on this? Replyabufrejoval - Wednesday, September 28, 2022 - link
Emerging dGPUs not supporting PCIe 5.0 is just crippleware!While I can easily see that 16 lanes of PCIe 5.0 won't do much for any game, I can very much see what I'd do with the 8 lanes left over when all dGPU bandwidth requirements can be met with just 8 lanes of PCIe 5.0.
Why can't they just be good PCIe citizens and negotiate to use 16 lanes of PCIe 4.0 on lesser or previous generation boards and optimize lane allocation on higher end PCIe 5.0 systems that can then use bifurcation to add say a 100Gbit NIC, plenty of Thunderbolt 4 or better yet, something CXL?
Actually I'd be really astonished if this wasn't even an artifical cap and that the Nvidia chips may actually be able to do PCIe 5.0.
It's just that they'd much rather have people use NVlink. Reply
TheinsanegamerN - Tuesday, October 4, 2022 - link
Um....dude, 4.0x16 and 5.0x8 have the same bandwidth, and no GPU today can saturate 4.0, not even close. The 300ti OCed manages to saturate.....2.0. 3.0 is a whopping 7% faster.You got awhile man. Reply
abufrejoval - Wednesday, September 28, 2022 - link
It should be interesting to see if AMD is opening the architecture for 3rd parties to exploit the actual potential of the Ryzen 7000 chips.The current mainboard/slot era that dates back to the 1981 IBM-PC (or the Apple ][) really is coming to an end and perhaps few things highlight this as well as a 600 Watt GPU that has a 65 Watt mainboard hanging under it.
We may really need something more S100 or VME, for those old enough to understand that.
Thunderbolt cables handle 4 lanes of PCIe 3.0 today and AFAIK cables are used for much higher lane counts and PCIe revisions within high-end server chassis today, even if perhaps at shorter lengths and with connectors designed for somewhat less (especially less frequent) pluggability.
Their main advantage is vastly reduced issues with mainboard traces and much better use of 3D space to optimize air flow cooling.
Sure those cables aren't cheap, but perhaps the cross-over point for additional PCB layers has been passed. And optical interconnects are waiting in the wings: they will use cables, too.
You stick PCIe 5.0 x4 fixed length cables out from all sides of an AM5 socket and connect those either to high bandwidth devices (e.g. dGPU) or a switch (PCIe 5.0 variant of the current ASMedia), you get tons of flexibility and expandability in a box form factor, that may not resemble an age old PC very much, but deliver tons of performance and expandability in a deskside form factor.
You want to recycle all your nice PCIe 3.0 2TB NVMe drives? Just add a board that puts a PCIe 5.0 20 lane switch between (even PCIe 4.0 might do fine if it's 50% $$$).
And if your dGPU actually needs 8 lanes of PCIe 5.0 to deliver top performance, connect two of those x4 cables to undo a bit of bifurcation!
How those cable connected board would then mount in a chassis and be cooled across a large range of form factors and power ranges is up for lots of great engineers to solve, while dense servers may already provide lots of the design bricks.
Unfortunately all that would require AMD to open up the base initialization code and large parts of the BIOS, which I guess currently has the ASmedia chip(s) pretty much hardwired into it.
And AMD with all their "we don't do artificial market segmentation" publicity in the past, seem to have become far more receptive to its bottom line benefits recently, to allow a free transition from console to PC/workstation and servers of all sizes.
And it would take a high-volume vendor (or AMD itself), a client side Open Compute project or similar to push that form factor the the scale where it becomes economically viable.
It's high time for a PC 2.0 (which isn't a PS/2) to bridge into the CXL universe even on desktops and workstations. Reply
Oxford Guy - Wednesday, September 28, 2022 - link
"The current mainboard/slot era that dates back to the 1981 IBM-PC (or the Apple ][)"Absolutely nothing about the IBM PC was new. The Micral N introduced slots in a microcomputer and the S-100 bus, introduced by the Altair, became the first big standard. Reply