The Apple A15 SoC Performance Review: Faster & More Efficient
by Andrei Frumusanu on October 4, 2021 9:30 AM EST- Posted in
- Mobile
- Apple
- Smartphones
- Apple A15
Conclusion & End Remarks
Today’s investigation into the new A15 is just scratching the tip of the iceberg of what Apple has to offer in the new generation iPhone 13 series devices. As we’re still working on the full device review, we got a good glimpse of what the new silicon is able to achieve, and what to expect from the new devices in terms of performance.
On the CPU side of things, Apple’s initial vague presentation of the new A15 improvements could either have resulted in disappointment, or simply a more hidden shift towards power efficiency rather than pure performance. In our extensive testing, we’re elated to see that it was actually mostly an efficiency focus this year, with the new performance cores showcasing adequate performance improvements, while at the same time reducing power consumption, as well as significantly improving energy efficiency.
The efficiency cores of the A15 have also seen massive gains, this time around with Apple mostly investing them back into performance, with the new cores showcasing +23-28% absolute performance improvements, something that isn’t easily identified by popular benchmarking. This large performance increase further helps the SoC improve energy efficiency, and our initial battery life figures of the new 13 series showcase that the chip has a very large part into the vastly longer longevity of the new devices.
In the GPU side, Apple’s peak performance improvements are off the charts, with a combination of a new larger GPU, new architecture, and the larger system cache that helps both performance as well as efficiency.
Apple’s iPhone component design seems to be limiting the SoC from achieving even better results, especially the newer Pro models, however even with that being said and done, Apple remains far above the competition in terms of performance and efficiency.
Overall, while the A15 isn’t the brute force iteration we’ve become used to from Apple in recent years, it very much comes with substantial generational gains that allow it to be a notably better SoC than the A14. In the end, it seems like Apple’s SoC team has executed well after all.
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repoman27 - Monday, October 4, 2021 - link
By 2023 Apple SoCs will likely include integrated 5G, seeing as they spent $1B to acquire Intel’s modem division. Until then, Qualcomm discrete is really their only option.cha0z_ - Tuesday, October 5, 2021 - link
As said - no integrated modem is entirely doing of qualcomm. Won't last long tho, apple are already deep into designing their own 5G modem ;)5j3rul3 - Monday, October 4, 2021 - link
Will anandtech review iPad mini 2021 and iPad Pro 12.9 2021?Andrei Frumusanu - Monday, October 4, 2021 - link
Currently we have no plans on the iPads, no.5j3rul3 - Monday, October 4, 2021 - link
Thank you!name99 - Monday, October 4, 2021 - link
I would be curious if you at least ran the latency tests on an M1 device, to compare.That would allow us to perhaps understand how the L2 is split.
Right now one can imagine at least three possibilities:
- drowsy cache with three or four segments (usually you do this by sleeping some fraction of the ways), so that as you go larger some fraction of the time you are hitting a drowsy segment more often and taking an extra cycle
- virtual L3. ie each core gets half the L2, and some fraction (again likely by way) of the L2 "attached" to the other core is treated as virtual L3
- your hypothesis for the A13 that some fraction of the L2 was (either absolutely, or effectively in terms of the heuristics used) locked to use by the E cores
If we has curves for M1 (with 4 rather than 2 P clients) the relative fractions at each size might serve to stengthen vs weaken among these options.
Andrei Frumusanu - Monday, October 4, 2021 - link
We had run latency on M1 when I still had it; https://images.anandtech.com/doci/16252/latency-m1...It obviously looks quite different. I've determined before that Apple does some logical partitioning of the caches, it's a bit hard to measure one core while the other does something.
name99 - Monday, October 4, 2021 - link
Thanks for the plot!That seems to show jumps at 3MB and 6MB, which does suggest a per-core split (whether logical or physical, who knows; does the question even have any real meaning?).
I can make up a model for it (each cache gets 3MB of L2, other core's L2 can be used as virtual L2, each of the 3MB is split into three segments that are independently drowsy) which kinda fits what we see, and which one can kinda retrofit to the A14 graph.
I'm always loathe to blame "energy saving" for weird anomalies; in this case drowsy cache. But it's not a completely crazy hypothesis. On the other hand, we know that the SLC is also drowsy (thought at a rather finer granularity) and yet we don't see an obvious jump signature of drowsiness there (though maybe we wouldn't, given the fine granularity; just a steady ramp in mean access time?)
I could imagine that the way the split works is something like half the tags, and so half the way's are "allocated" to one core rather than the other. If you find the result in "your" tag lookup, great; if not, lose a cycle and look in the tags of the other core(s)? Would mostly work well, uses lower energy, and you only have to pay the occasional extra tag lookup(s) when you're sharing data or code with another core.
This would imply that you could see a signature of the effect by investigating how many ways the cache presents. It should appear to present say 4 fast ways and 4 slower ways (or 3 fast ways and 9 slower ways for 4 cores). One more thing to add to the list of stuff to experiment with!
5j3rul3 - Monday, October 4, 2021 - link
Hope there's display efficiency measurements for iPhone 13 and iPhone 13 pro's displayAnd, I'm so curious that why there's no 60 Hz VRR smartphones?
5j3rul3 - Monday, October 4, 2021 - link
The iPhone's VRR is interesting I think, and hope some detailed analysis on it.