Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed
by Dr. Ian Cutress & Andrei Frumusanu on August 19, 2021 9:00 AM ESTInstruction Sets: Alder Lake Dumps AVX-512 in a BIG Way
One of the big questions we should address here is how the P-cores and E-cores have been adapted to work inside a hybrid design. One of the critical aspects in a hybrid design is if both cores support different levels of instructions. It is possible to build a processor with an unbalanced instruction support, however that requires hardware to trap unsupported instructions and do core migration mid-execution. The simple way to get around this is to ensure that both types of cores have the same level of instruction support. This is what Intel has done in Alder Lake.
In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled.
Intel’s journey with AVX-512 has been long and fragmented. Some workloads can be vectorised – multiple bits of consecutive data all require the same operation, so you can pack them into a single register and perform it all at once with a single instruction. Designed as its third generation of vector instructions (AVX is 128-bit, AVX2 is 256-bit, AVX512 is 512-bit), AVX-512 was initially found on server processors, then mobile, and we found it in the previous version of desktop processors. At the time, Intel stated that by enabling AVX-512 on its processor line from top to bottom, it would encourage greater adoption, and they were leaning hard into this missive.
But that all changes with Alder Lake. Both desktop processors and mobile processors will now have AVX-512 disabled in all scenarios. But the silicon will still be physically present in the core, only because Intel uses the same core in its next generation server processors called Sapphire Rapids. One could argue that if the AVX-512 unit was removed from the desktop cores that they would be a lot smaller, however Intel has disagreed on this point in previous launches. What it means is that for the consumer parts we have some extra dark silicon in the design, which ultimately might help thermals, or absorb defects.
But it does mean that AVX-512 is probably dead for consumers.
Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512.
On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2. In testing with the previous generation Tremont Atom core, at 2.9 GHz it performed similarly to a Haswell 2.9 GHz Celeron processor, i.e. identical in non-AVX2 situations. By adding AVX2, plus fundamental performance increases, we’re told to expect ‘Skylake-like performance’ from the new E-cores. Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support.
By enabling AVX2 on the E-cores, Intel is also integrating support for VNNI instructions for neural network calculations. In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake. So while AVX-512 might be dead here, at least some of those AI acceleration features are carrying over, albeit in AVX2 form.
For the data center versions of these big cores, Intel does have AVX-512 support and new features for matrix extensions, which we will cover in that section.
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mode_13h - Thursday, August 19, 2021 - link
> On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2.Finally. It's about f'ing time, Intel.
> desktop processors and mobile processors will now have AVX-512 disabled in all scenarios.
> ...
> If AMD’s Zen 4 processors plan to support some form of AVX-512 ... we might be in
> some dystopian processor environment where AMD is the only consumer processor
> on the market to support AVX-512.
LOL! Exactly! I wouldn't call it "dystopian", exactly. Just paradoxical.
And now that Intel has been pushing AVX-512 adoption for the past 5 years, there should actually be a fair amount of software & libraries that can take advantage of it, making this the worst possible time for Intel to step back from AVX-512! Oh, the irony would be only too delicious!
> Intel is also integrating support for VNNI instructions for neural network calculations.
> In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel
> has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake.
Wow. That really says a lot about what a discombobulated mess the development of Alder Lake must've been! They thought the E-cores would be a good area-efficient way to add performance, but then AVX-512 probably would've spoiled that. So, then they had to disable AVX-512 in the P-cores. But, since that would hurt deep learning performance too much, they had to back-port VNNI to AVX2!
And then, we're left to wonder how much software is going to bother supporting it, just for this evolutionary cul-de-sac of a CPU (presumably, Raptor Lake or Meteor Lake will finally enable AVX-512 in the E-cores).
Gondalf - Thursday, August 19, 2021 - link
Have you realized this SKU was thinked for 7nm ??....and than backported to 10nm ???.Rocket Lake number two.
TomWomack - Thursday, August 19, 2021 - link
VNNI is four very straightforward instructions (8-bit and 16-bit packed dot-product with/without saturation), so the back port is unlikely to have been difficultmode_13h - Thursday, August 19, 2021 - link
Yeah, but it implies some chaos in the design process.Also, my question about how well-supported it will be stands. I think a lot of people aren't going to go back and optimize their AVX2 path to use it. Any focus on new instructions is likely to focus on AVX-512.
Spunjji - Monday, August 23, 2021 - link
If they kill AVX-512 in consumer with ADL only to bring it back in the next generation, I shall be laughing a hearty laugh. Another round of "developer relations" funding will be needed...Personally I think they never should have brought it to consumer.
mode_13h - Tuesday, August 24, 2021 - link
> I think they never should have brought it to consumer.I have my gripes against AVX-512 (mostly, with regard to the 14 nm implementation), but it's not all bad. I've read estimates that it only adds 11% to the core size of Skylake-SP (excluding the L3 cache slice & such). It was estimated at about 5% of a Skylake-SP compute tile. So, that means less than 5% of the total die size. So, it's probably not coming at too high a price.
Spunjji - Friday, August 27, 2021 - link
That's fair - my reasons for thinking they shouldn't have done it are more related to marketing and engineering effort than die space, though.They put in a lot of time and money to bring a feature to a market that didn't really need it, including doing a load of "developer relations" stuff to develop some cringe-worthy edge-case benchmark results, alongside a bunch of slightly embarrassing hype (including the usual sponsored posters on comment sections), all to lead up to this quiet little climb-down.
Seems like to me like it would have made more sense to designate it as an Enterprise Grade feature - an excuse to up-sell from the consumer-grade "Xeon" processors - and then trickle it down to consumer products later.
mode_13h - Saturday, August 28, 2021 - link
> Seems like to me like it would have made more sense to designate it as an Enterprise> Grade feature ... and then trickle it down to consumer products later.
Yeah, that's basically what they did. They introduced it in Skylake-SP (if we're not counting Xeon Phi - KNL), and kept it out of consumers' hands until Ice Lake (laptop) and Rocket Lake (desktop). It seems pretty clear they didn't anticipate having to pull it back, in Alder Lake, when the latter two were planned.
mode_13h - Saturday, August 28, 2021 - link
BTW, you know the Skylake & Cascade Lake HEDT CPUs had it, right? So, the whole up-sell scheme is what they *actually* did!TristanSDX - Thursday, August 19, 2021 - link
If ADL have disbaled features like part of L2 cache or without AVX-512, so it is interesting if presented 19% IPC growth apply to ADL or SPR.AMD Zen 3 will definitelly have AVX-512, BIG shame on you, for disabling it, even for SKU without small cores