Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed
by Dr. Ian Cutress & Andrei Frumusanu on August 19, 2021 9:00 AM ESTInstruction Sets: Alder Lake Dumps AVX-512 in a BIG Way
One of the big questions we should address here is how the P-cores and E-cores have been adapted to work inside a hybrid design. One of the critical aspects in a hybrid design is if both cores support different levels of instructions. It is possible to build a processor with an unbalanced instruction support, however that requires hardware to trap unsupported instructions and do core migration mid-execution. The simple way to get around this is to ensure that both types of cores have the same level of instruction support. This is what Intel has done in Alder Lake.
In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled.
Intel’s journey with AVX-512 has been long and fragmented. Some workloads can be vectorised – multiple bits of consecutive data all require the same operation, so you can pack them into a single register and perform it all at once with a single instruction. Designed as its third generation of vector instructions (AVX is 128-bit, AVX2 is 256-bit, AVX512 is 512-bit), AVX-512 was initially found on server processors, then mobile, and we found it in the previous version of desktop processors. At the time, Intel stated that by enabling AVX-512 on its processor line from top to bottom, it would encourage greater adoption, and they were leaning hard into this missive.
But that all changes with Alder Lake. Both desktop processors and mobile processors will now have AVX-512 disabled in all scenarios. But the silicon will still be physically present in the core, only because Intel uses the same core in its next generation server processors called Sapphire Rapids. One could argue that if the AVX-512 unit was removed from the desktop cores that they would be a lot smaller, however Intel has disagreed on this point in previous launches. What it means is that for the consumer parts we have some extra dark silicon in the design, which ultimately might help thermals, or absorb defects.
But it does mean that AVX-512 is probably dead for consumers.
Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512.
On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2. In testing with the previous generation Tremont Atom core, at 2.9 GHz it performed similarly to a Haswell 2.9 GHz Celeron processor, i.e. identical in non-AVX2 situations. By adding AVX2, plus fundamental performance increases, we’re told to expect ‘Skylake-like performance’ from the new E-cores. Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support.
By enabling AVX2 on the E-cores, Intel is also integrating support for VNNI instructions for neural network calculations. In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake. So while AVX-512 might be dead here, at least some of those AI acceleration features are carrying over, albeit in AVX2 form.
For the data center versions of these big cores, Intel does have AVX-512 support and new features for matrix extensions, which we will cover in that section.
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mode_13h - Friday, August 20, 2021 - link
> they can't exactly prevent open source software from developingWell, they don't have to release all of the information that would be needed for Linux to do the same thing.
> Linux will probably have better support than Windows itself
Intel is one of the largest contributors to the Linux kernel. No doubt, any support for their Thread Director will be developed by them.
Obi-Wan_ - Thursday, August 19, 2021 - link
Is it likely that Alder Lake will consume noticeably less power when near idle or during video playback/streaming, or are existing CPUs already quite efficient in these cases?I'm thinking an HTPC that should be as silent as possible when idling and streaming, but also have a high power budget (effectively noise budget) when gaming for example.
mode_13h - Friday, August 20, 2021 - link
If you really care about minimizing idle power, then I think you probably need to use LPDDR memory. Integrated graphics should also be a priority.Another thing people miss is that the PSU should not only be a high-efficiency model, but also not heavily over-spec'd. Power supplies lose a lot of efficiency, when you run them well below peak load.
mode_13h - Thursday, August 19, 2021 - link
> The desktop processor will have sixteen lanes of PCIe 5.0I'll believe it when I see it. Let's not forget that it took Intel 2 generations to get PCIe 4.0 working! They had to reverse course on enabling it it Comet Lake, and that was years after POWER, Ryzen, and some ARM CPUs had it.
I also don't see the value of having it now, given that we know DG2 is going to be only PCIe 4, nor are we aware of any other upcoming GPUs that will support 5.0.
Bp_968 - Sunday, August 22, 2021 - link
Pcie 5 is twice as fast and backwards compatible. Why would you *not* want it in your system if possible? Its not like you can add it later.Pcie4 is mostly useless for gpus already (regardless if they "support" it or not) so pcie5 isnt going to improve anything gpu wise just like it didnt improve with pcie4.
But where it *will* be an improvement is in peripherals (the x4 channel to the chipset just got twice as fast) and support for pcie5 storage. Oh and easier support for high speed interconnects like USB 3-4 and 10gb ethernet.
Personally id prefer the layout be different. X16 or X8/x8 (plus 2 x4 slots for nvme i think) for the pcie5 is ok, but on the pcie4 side I'd like to see x16, x8/x8 as an option as well. That way you could use the pcie5 slots on other stuff and put the gpu in a x16 or x8 pcie4 slot (and it perform just as well). Support for 4+ nvme drives will be nice in the future. One or two pcie5 high speed units and then spots for slower SSDs for mass storage (x2 or x4 pcie4 being the "slow" slots).
mode_13h - Monday, August 23, 2021 - link
> Pcie 5 is twice as fast and backwards compatible.> Why would you *not* want it in your system if possible?
Mainly due to board and peripheral costs, I think. Beyond that, power dissipation should be well above PCIe 4.0 and it could also be a source of stability issues.
> But where it *will* be an improvement is in peripherals
> (the x4 channel to the chipset just got twice as fast)
This is actually the one place where it makes sense to me. The chipset can be located next to the CPU, so that hopefully no retimers will be needed. And the additional power needed to run a short x4 link @ 5.0 speeds hopefully shouldn't be too bad. When leaks first emerged about Alder Lake having PCIe 5.0, I suspected it was just for the chipset link.
> support for pcie5 storage.
By the time there are any consumer SSDs that exceed PCIe 4.0 x4 speeds, we'll already be on a new platform. It took over a year for PCIe 4.0 SSDs to finally surpass PCIe 3.0 x4 speeds, and many still don't.
> easier support for high speed interconnects like USB 3-4
The highest-rated speed for USB4 is PCIe 3.0 x4. However, even a chipset link of PCIe 4.0 x4 will mean you can support it with bandwidth to spare. That said, I think the highest-speed USB links are typically CPU-direct, in recent generations.
> 10gb ethernet.
You can already do that with a PCIe 4.0 x1 link.
Spunjji - Monday, August 23, 2021 - link
> But where it *will* be an improvement is in peripherals> (the x4 channel to the chipset just got twice as fast)
It doesn't use PCIe 5.0 for the chipset link, so it doesn't even have that advantage. I genuinely think it's premature. I guess we'll have to see what motherboard costs look like to know whether it was worth it for future-proofing, or whether it's just spec wankery.
mode_13h - Tuesday, August 24, 2021 - link
> It doesn't use PCIe 5.0 for the chipset linkI'm pretty sure they didn't specify that, one way or another. I'm pessimistic, though. Then again, didn't Rocket Lake have a PCIe 4.0 x8 link to the chipset? If so, moving up to PCIe 5.0 x4 is plausible.
> or whether it's just spec wankery.
It's definitely wankery. I'm just waiting for them either to walk it back, a la Comet Lake's PCIe 4.0 support, or for users to encounter a raft of issues, once some PCIe 5.0 GPU is finally released and people try to actually *use* the capability.
Spunjji - Friday, August 27, 2021 - link
All the resources I'm finding online say it's a DMI 4.0 x8 link to the chipset, so the same as Rocket Lake. Personally I think that's going to be plenty for the vast majority of their users, assuming they follow up at some point in the not-too distant future with an up-to-date HEDT platform for the users who need more.mode_13h - Saturday, August 28, 2021 - link
That's a shame, because the DMI link is the one place where Intel could've gotten practical benefits from using PCIe 5.0, right away.