Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed
by Dr. Ian Cutress & Andrei Frumusanu on August 19, 2021 9:00 AM ESTInstruction Sets: Alder Lake Dumps AVX-512 in a BIG Way
One of the big questions we should address here is how the P-cores and E-cores have been adapted to work inside a hybrid design. One of the critical aspects in a hybrid design is if both cores support different levels of instructions. It is possible to build a processor with an unbalanced instruction support, however that requires hardware to trap unsupported instructions and do core migration mid-execution. The simple way to get around this is to ensure that both types of cores have the same level of instruction support. This is what Intel has done in Alder Lake.
In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled.
Intel’s journey with AVX-512 has been long and fragmented. Some workloads can be vectorised – multiple bits of consecutive data all require the same operation, so you can pack them into a single register and perform it all at once with a single instruction. Designed as its third generation of vector instructions (AVX is 128-bit, AVX2 is 256-bit, AVX512 is 512-bit), AVX-512 was initially found on server processors, then mobile, and we found it in the previous version of desktop processors. At the time, Intel stated that by enabling AVX-512 on its processor line from top to bottom, it would encourage greater adoption, and they were leaning hard into this missive.
But that all changes with Alder Lake. Both desktop processors and mobile processors will now have AVX-512 disabled in all scenarios. But the silicon will still be physically present in the core, only because Intel uses the same core in its next generation server processors called Sapphire Rapids. One could argue that if the AVX-512 unit was removed from the desktop cores that they would be a lot smaller, however Intel has disagreed on this point in previous launches. What it means is that for the consumer parts we have some extra dark silicon in the design, which ultimately might help thermals, or absorb defects.
But it does mean that AVX-512 is probably dead for consumers.
Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512.
On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2. In testing with the previous generation Tremont Atom core, at 2.9 GHz it performed similarly to a Haswell 2.9 GHz Celeron processor, i.e. identical in non-AVX2 situations. By adding AVX2, plus fundamental performance increases, we’re told to expect ‘Skylake-like performance’ from the new E-cores. Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support.
By enabling AVX2 on the E-cores, Intel is also integrating support for VNNI instructions for neural network calculations. In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake. So while AVX-512 might be dead here, at least some of those AI acceleration features are carrying over, albeit in AVX2 form.
For the data center versions of these big cores, Intel does have AVX-512 support and new features for matrix extensions, which we will cover in that section.
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Gondalf - Thursday, August 19, 2021 - link
You mean 5nm Zen 4 will have AVX512.Anyway wait and see if only on server cores or even in consumer, sure 5nm will give room for AVX512 in desktop cpus, but it is not for certain.
The funny thing we are in front of a tight situation for both Intel and AMD.
AMD can not go seriously on 5nm because there are not enough wafers around, Intel have to wait 7nm for new designs.
Intersting times, if roadmaps are true, both AMD and Intel will are on a 5nm class process around at the same time, sometime at the end of 2022.
We'll see the best one between two contenders.
JayNor - Thursday, August 19, 2021 - link
Looks like a Sapphire Rapids HEDT would be Intel's solution for pro consumers who want avx512. It would include bfloat16 support and AMX tiled matrix operations, which have not been available previously.An eight core Golden Cove HEDT chip with its dual avx512 and tiled matrix bfloat16 units enabled sounds like a decent upgrade from Ice Lake HEDT.
mode_13h - Friday, August 20, 2021 - link
Does SPR have BFloat16 in AVX-512, or just via AMX? I thought its AVX-512 is still not fully caught up with Cooper Lake.Kamen Rider Blade - Thursday, August 19, 2021 - link
The desktop processor will have sixteen lanes of PCIe 5.0, which we expect to be split as x16 for graphics or as x8 for graphics and x4/x4 for storage. This will enable a full 64 GB/s bandwidth. Above and beyond this are another four PCIe 4.0 lanes for more storage. As PCIe 5.0 NVMe drives come to market, users may have to decide if they want the full PCIe 5.0 to the discrete graphics card or notWhy won't they allow BiFurication of PCIe 5.0 = x12 + x4 as an option?
x12 PCIe lanes is part of the PCIe spec, it should be better supported.
Same with PCIe Gen 5.0 x12 + x2 + x2
That can offer alot of flexibility in end user setups.
mode_13h - Friday, August 20, 2021 - link
The reality is that consumers don't need PCIe 5.0 x16. The benefits of even 4.0 x16 are small (but certainly real, in several cases).IMO, the best case for PCIe 5.0 would be x8 + x8 for multi-GPU setups. This lets you run dual-GPU, with each getting the same bandwidth as if it had a 4.0 x16 link.
Unfortunately, they seem to have overlooked that obvious win, and all for the sake of supporting a use case we certainly won't see within the life of this platform: a SSD that can actually exceed 4.0 x4 speeds.
Dug - Friday, August 20, 2021 - link
As long as I can have 3 ssd's that can run full speed at PCIe 4.0, I'll be happy.mode_13h - Thursday, August 19, 2021 - link
The Thread Director is intriguing. I wonder how much of the same information can be gleaned from the performance counter registers, although having an embedded microcontroller analyze it saves the OS from the chore of doing so.Can it raise interrupts, though? If not, then I don't see much point to enabling performance characterization in 30 microseconds, as that's way shorter than an OS timeslice.
It should be an interesting target for new sidechannel attacks, as well.
Jorgp2 - Thursday, August 19, 2021 - link
Isn't it hardware feedback interface, not hardware frequency interface?eastcoast_pete - Thursday, August 19, 2021 - link
To me, the star of the CPU cores is the "little" one, Gracemont. Question about AL in Ultrabooks: Why not an SoC with 4, 6, or 8 Gracemont cores plus some Xe Graphics, at least for the lower end? For most regular business use cases, that'll do just fine. The addition of AVX/AVX2 also means that certain effects for video conferencing, such as virtual backgrounds (Teams, other) is now possible with these beefed-up Atoms.And, on the other end of the spectrum, I agree with Ian that a 32 or more Gracemont-core CPU would work well if you want to run a lot of threads within a reasonable power envelope. @Ian: any chance you can get your hands on one of the CPUs specified for 5G base stations? Even the current, Tremont-based ones are exactly that: many Atom cores in one, specialized server CPU. Would be nice to see how those go.
eastcoast_pete - Thursday, August 19, 2021 - link
To be very precise: I meant an SoC without any "Cove" cores, just 4 or more Gracemonts. It'll do for many, especially business uses.