Conclusion & First Impressions

Today’s Arm Client TechDay disclosures were generally quite a lot more extensive than in the last few years, especially given the number of new IP releases we’ve covered. Three new CPU microarchitectures, a new DSU/L3 cluster design, and two new SoC interconnect IPs is quite a bit more than we’re used to, and it goes to underscore just how much effort Arm is putting into updating all of the parts of its client IP.

Starting off with the CPUs, the new Cortex-X2 and Cortex-A710 cores are meant to be iterative designs compared to their predecessors, and that's certainly what they are from a performance and efficiency viewpoint. On a generational basis, Arm is promising a 10-16% improvement in IPC. However these figures are somewhat muddled by the fact we’re also comparing 4MB and 8MB L3 caches. Generally, it’s a reasonable expectation of what we’ll be seeing in 2022 devices, but it’s also hard to disambiguate and attribute the performance of the cores versus that of the new DSU-110 L3 cluster design.

Arm has also made some more lofty performance claims when it comes to actual device implementations in 2022, such as +30% peak-to-peak performance boosts on the parts of the X2 cores. Generally, given our expectations that both the next Snapdragon and the next Exynos flagships will come in a similar Samsung foundry process node with smaller improvements, I’m very doubtful we’ll be seeing such larger generational improvements in practice, unless somehow MediaTek surprises us with a flagship X2 SoC made out at TSMC.

While the X2 and A710 aren’t all that groundbreaking, we have to note that the move towards Armv9 brings a lot of new architectural features that would otherwise eat into the expected yearly performance or efficiency improvements. The move to the new ISA baseline has been a long time coming and I’m curious to see what it will enable in terms of media applications (SVE) or AI (new ML instructions).

This is also the fourth and last iteration of Arm’s Austin core family, so hopefully next year’s new Sophia family will see larger generational leaps. Arm admits that we’re nearing diminishing returns and it’s certainly not at the same break-neck pace it was moving a few years ago, but there’s still a lot which can be done.

Today we also saw the unveiling of a brand-new little core in the form of the Cortex-A510. A new clean-sheet design from the Cambridge team, it’s certainly using an innovative approach given its “merged core” design, sharing the L2 cache hierarchy and the FP/SIMD back-end amongst two otherwise full featured cores. The performance and IPC gains are claimed to be quite large at +35-50%, however it seems that this generation hasn’t improved the efficiency curve all that much. It’s still a much better design and will have effective benefits for power efficiency in real-world workloads due to how workloads interact between the little and larger cores, but leaves us with a feeling that it doesn’t provide a knock-out convincing jump we had expected after 4 years. The silver lining here is that Arm is promising further generational improvements in performance and power with subsequent iterations, so we won’t be left with the current state of affairs the same way we saw the Cortex-A55 stagnate.

One of the more key points I saw Arm put their focus on was the new possibilities in larger form-factor devices beyond mobile. The new DSU-110 now supports up to 8 Cortex-X2 cores, a theoretical setup that would pretty much blow away the current Cortex-A76 based Arm laptop SoCs such as the Snapdragon 8cx family. The new cluster design allows for large L3 caches of up to 16MB, and while I don’t know if we’ll see the new interconnect IPs used by the larger vendors, it surely also makes a big argument for larger performance designs. The catch is that if Qualcomm were to adopt and make such a design, it would seemingly be short-lived given their recent Nuvia acquisition and intent on using custom cores. Otherwise, because of a lack of Mali Windows drivers, this really only leaves space for a theoretical Samsung laptop SoC with AMD RDNA GPU, but such a SoC could nonetheless be very successful.

Overall, this year’s CPU and system IP announcements from Arm are extremely solid new IP offerings, really laying down a new foundation, both architecturally with Armv9, and microarchitecturally thanks to elements such as the new DSU and the new little core CPUs. We’re looking forward to the new 2022 SoCs and products that will be powered by the new Arm IP.

A new CI-700 Coherent Interconnect & NI-700 NoC For SoCs
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  • Spunjji - Thursday, May 27, 2021 - link

    Comments saying "x86 is dead" are just as daft as the comments declaring that ARM will never be a threat to x86.
  • mode_13h - Tuesday, May 25, 2021 - link

    What a terrible naming scheme!

    If they didn't want to just start from a blank slate, they should've gone on to letters. So, A7A and A5A.

    Also, given that the X-cores are typically going to be paired with their cousin A-series core, the naming scheme should reflect that relationship. So, maybe the X1 should've been the X78 and the X2 could be the X710 or X7A.
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, why skip 9? A59 and A79 would be a great mnemonic for the first mobile cores to be ARMv9!
  • nandnandnand - Tuesday, May 25, 2021 - link

    I'm fine with the naming scheme.

    For the Cortex-X line, they can just do X1, X2, X3, X4... X-cetera.

    For these new ones, A710 and A510 are the baseline, and they can put out A720, A525, or whatever until they run it up to A799. That could take over a decade if they don't increment the numbers so much. The '7' and '5' let you know these are related to the A78/A55, and the 3 digits lets you know it's part of the brave new world of ARMv9.
  • mode_13h - Tuesday, May 25, 2021 - link

    > they can put out A720

    That could potentially create some confusion about the relationship between A72 and A720.

    > 3 digits lets you know it's part of the brave new world of ARMv9.

    Okay, so create a new numbering scheme! No need to piggy back off the old one, if it's "a brave new world", right?
  • phoenix_rizzen - Tuesday, May 25, 2021 - link

    Would have been a good time to pick new letters. Leave Cortex-A, Cortex-X, Cortex-M etc for Armv8.x.

    Even better, drop the Cortex name, and pick something new for Armv9-based cores.

    X, Y, Z would have been nice for big, middle, little cores.

    Ah well, marketing-droids will do what marketing-droids do. :D
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, A79 would line up nicely with being the last generation of this microarchitecture family.

    Then, maybe the "Sophia" cores could start a new numbering series.
  • GeoffreyA - Thursday, May 27, 2021 - link

    "What a terrible naming scheme!"

    They should battle it out with Intel's Marketing arm to see who's the best in the field of naming.
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    Disappointed in the design choice of the new LITTLE cores. I have the strong suspicion that the IPC comparison of the 510 LITTLE core to the A73 (the 510 getting close to the A73) is with one 510 core per complex, maximal cache and cache bandwidth etc, which, of course, is highly theoretical. After all, the 510s are designed to come in pairs sharing resources for a reason. I am underwhelmed by this design, ARM's own power/perf curves show very little if any difference to A55 until one gets to the high end of the power curve, at which point the 710 big cores would have taken over. Unfortunately, Apple's power/perf crown for efficiency cores remains quite and comfortably safe. As an Android user, however, I remain stuck with ARM's designs, as none of the design houses (QC, Samsung) is even attempting custom core designs for smartphone SoCs. We are seeing the downside of a monopoly here
  • mode_13h - Tuesday, May 25, 2021 - link

    > I remain stuck with ARM's designs, as none of the design houses (QC, Samsung)
    > is even attempting custom core designs for smartphone SoCs.

    Qualcomm is saying they're using their Nuvia acquisition to make new mobile cores.

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