Intel today has announced that the company will be holding an event on March 23rd to discuss the future of engineering at the company. Dubbed “Intel Unleashed: Engineering the Future”, the hour-long webcast will be hosted by recently hired CEO (and Intel returnee) Pat Gelsinger.

Join Intel CEO Pat Gelsinger for a business update and webcast address on the new era of innovation and technology leadership at Intel.

While Intel’s official description is short and at a high level, given the subject matter and the fact that the presentation is scheduled for after the stock markets close, we’re expecting that this will be Intel’s much-awaited announcement on the future of the company’s manufacturing plans. For the last several months the company has been juggling the question of when and where to use third-party foundries versus investing in their own manufacturing technologies. Intel’s 7nm problems have become a black eye for the company, and the prolific processor producer has been under pressure from some investors to cut back on expensive R&D and just use pure-play foundries like TSMC.

Prior to Intel hiring Gelsinger to be their new CEO in mid-January, the company had been preparing to detail its future foundry plans in its January 21st earnings call. However after bringing Gelsinger on board, that announcement was put on hold to give Gelsinger a time to get up to speed, and possibly make his own mark if he decided to take the company in a different direction than then-CEO BoB Swan was preparing to go.

If this does turn out to be a detailed disclosure of Intel’s foundry plans, then it’s not an exaggeration to say that this webcast will be one of the most critical Intel presentations in years. Gelsinger and the rest of Intel’s upper management have some very difficult choices to make about manufacturing, and no matter what direction they opt to take on Tuesday, it’s going to have significant ramifications for not only Intel, but the rest of the silicon foundry industry as a whole. So tech enthusiasts and investors alike are going to be paying close attention to this announcement.

Source: Intel Newsroom

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  • tomatotree - Thursday, March 18, 2021 - link

    Intel has had a successor to the ring bus since 2017, and it was used on Skylake-SP: https://www.anandtech.com/show/11550/the-intel-sky... Reply
  • Oxford Guy - Thursday, March 18, 2021 - link

    'In Desktop maybe in games Rocketlake might get a few points'

    Not at the same power consumption.
    Reply
  • dsplover - Thursday, March 18, 2021 - link

    I wish them luck. They’ll need it as AMD is stealing more market share than anyone foresaw. Reply
  • Qasar - Thursday, March 18, 2021 - link

    not according to the pro intel fans Reply
  • shabby - Thursday, March 18, 2021 - link

    Microcode isn't final! Reply
  • Qasar - Sunday, March 21, 2021 - link

    doesnt really matter if it isnt final, it wont improve performance all that much, as the follow up article showed, it kind of brought tiger lake up to match 10th gen, but even then still looses to it in some tests, and still, over all, isnt faster then zen3. sorry shabby, but tiger lake, still looks to be a dud. Reply
  • Amandtec - Thursday, March 18, 2021 - link

    Intel may just be screwed because even if they move to TSMC, CISC chip development is known to be more difficult and costly. That RISC would eventually overtake CISC was predicted decades ago - I remember it being discussed in the 90's - now that AMD has the momentum, easier RISC development may carry them further and further away on IPC through regular iterative improvements. Reply
  • kgardas - Thursday, March 18, 2021 - link

    Wake up! Intel is doing RISC business since Pentium Pro in late '90s (and btw, AMD even early with their K5). Internally all their high-perf CPUs are high perf RISC CPUs. That they do not advertise internal ISA and that they translate venerable x86/amd64 ISA to it is another matter. Reply
  • GeoffreyA - Thursday, March 18, 2021 - link

    The main bottleneck in x86 CPUs are the variable-length instructions, making parallel decoding difficult and eating a lot of power. The micro-op cache in Sandy Bridge and Zen has mitigated this to some extent; and marking instructions boundaries in cache---I believe K7 to Bulldozer, and Tremont---can help further. ARM has the advantage of fixed-length instructions, making it easy to work out where instructions begin, and as a result, one sees quite wide front ends on M1, for example. Reply
  • Matthias B V - Thursday, March 18, 2021 - link

    Hope we get lots of information on process and archs. I doubt he will talk about 5nm GAA but focus on 10nm+++ and 7nm.

    Still hope he is less of a bean counter and will go 7nm in 2022. Even if it is parallel to 10nm+++ / Enhanced Super Fin. They need to show they can and get expeience with EUV. Capacity and yield might be low but margin is secondary in my opinion. They can have a 2022 10nm RapotorLake from 5-125 Watt range for desktop and mobile and still sell 7nm MeteorLake in 5-35 Watt Mobile. They did the same with IceLake 10 / CometLake 14nm. And then progress fast to 5nm GAA same shared way in 2024. I do care less about densiy scaling than electical characteristics of GAA. By then they also would have enough EUV capacity which I dount they have in 2022. Not sure if they do as currently anything sells but that would be a short minded strategy if not.

    Also since they cant use their equioment from 22/14/10 nm DUV for 7nm EUV they could move most / some to 10nm and keep the rest to supply Automotive / IOT and get a additional customer base. Those processes are enough or that. Rather build new fabs for EUV and diversify.
    Reply

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