CPU Tests: Microbenchmarks

A y-Cruncher Sprint

The y-cruncher website has a large amount of benchmark data showing how different CPUs perform when calculating pi up to a given number of digits. Not only are the pi world records present, but below these there are a few CPUs showing the scaling of the hardware, where it shows the time to compute moving from 25 million digits to 50 million, 100 million, 250 million, and all the way up to 10 billion, to showcase how the performance scales with digits (assuming everything is in memory). This range of results, from 25 million to 250 billion, is something I’ve dubbed a ‘sprint’.

I have written some code in order to perform a sprint on every CPU we test. It detects the DRAM, works out the biggest value that can be calculated with that amount of memory, and works up starting from 25 million digits. For the tests that go up to the ~25 billion digits, it only adds an extra 15 minutes to the suite for an 8-core Ryzen CPU. With this test, we can see the effect of increasing memory requirements on the workload and the scaling factor for a workload such as this.

Longer lines indicate more memory installed in the system at the time

For this sprint, we’ve covered each result into how many million digits are calculated per second at each of the dataset sizes. The more cores a system has, the better the compute, and Intel gets an AVX-512 bonus here as well because the software can use AVX-512. But as the dataset gets larger, there is more shuffling of values back and forth between memory and cache, so being able to keep a high bandwidth while also a low latency to all cores is crucial in this test, especially as the test increases.

The 8-channel 64-core TR Pro 3995WX here does very well, peaking at around 80 million per second, and at the end of the test still being very fast. It sits above the EPYC 7742 here due to the fact that it has a higher TDP and frequency. They are both well above the Threadripper 3990X, which only has quad-channel memory, which is the reason for the decrease as the dataset increases.

The W-3175X from Intel has the AVX-512 advantage, which is why the 28 cores can compete with the 64 cores from AMD, however the six-channel memory bandwidth and probably the mesh quickly becomes a bottleneck as each core needs to feed those AVX-512 units. This is the sort of situation where in-package HBM is likely to make a big difference. But at the smaller dataset sizes at least the W-3175X can feed enough data across the mesh to the AVX-512 units for the peak throughput.

Core-to-Core Latency

As the core count of modern CPUs is growing, we are reaching a time when the time to access each core from a different core is no longer a constant. Even before the advent of heterogeneous SoC designs, processors built on large rings or meshes can have different latencies to access the nearest core compared to the furthest core. This rings true especially in multi-socket server environments.

But modern CPUs, even desktop and consumer CPUs, can have variable access latency to get to another core. For example, in the first generation Threadripper CPUs, we had four chips on the package, each with 8 threads, and each with a different core-to-core latency depending on if it was on-die or off-die. This gets more complex with products like Lakefield, which has two different communication buses depending on which core is talking to which.

If you are a regular reader of AnandTech’s CPU reviews, you will recognize our Core-to-Core latency test. It’s a great way to show exactly how groups of cores are laid out on the silicon. This is a custom in-house test built by Andrei, and we know there are competing tests out there, but we feel ours is the most accurate to how quick an access between two cores can happen.

Due to a test limitation, we’re only probing the first 64 threads of the system, but the scale out to 128 threads would be identical. This generation of Threadripper Pro is built on Zen 2, similar to Threadripper 3990X and the EPYC 7742, and so we only have quad-core CCXes in play here. A thread speaking to itself has a latency of around 7 nanoseconds, inside a quad-core CCX is around 18-19 nanoseconds, and then accessing any other core varies from 77-89 nanoseconds. Even accessing the CCX on the same chiplet has the same latency, as the communication is designed to ping out to the central IO die first. If Threadripper Pro gets boosted to Zen 3 for the next generation, this will be a big uplift as we’ve already seen with Zen 3. But TR Pro with Zen 3 might only be launched only when Zen 4 comes out, and we’ll be talking about that difference when that happens.

Frequency Ramping

Both AMD and Intel over the past few years have introduced features to their processors that speed up the time from when a CPU moves from idle into a high powered state. The effect of this means that users can get peak performance quicker, but the biggest knock-on effect for this is with battery life in mobile devices, especially if a system can turbo up quick and turbo down quick, ensuring that it stays in the lowest and most efficient power state for as long as possible.

Intel’s technology is called SpeedShift, although SpeedShift was not enabled until Skylake.

One of the issues though with this technology is that sometimes the adjustments in frequency can be so fast, software cannot detect them. If the frequency is changing on the order of microseconds, but your software is only probing frequency in milliseconds (or seconds), then quick changes will be missed. Not only that, as an observer probing the frequency, you could be affecting the actual turbo performance. When the CPU is changing frequency, it essentially has to pause all compute while it aligns the frequency rate of the whole core.

We wrote an extensive review analysis piece on this, called ‘Reaching for Turbo: Aligning Perception with AMD’s Frequency Metrics’, due to an issue where users were not observing the peak turbo speeds for AMD’s processors.

We got around the issue by making the frequency probing the workload causing the turbo. The software is able to detect frequency adjustments on a microsecond scale, so we can see how well a system can get to those boost frequencies. Our Frequency Ramp tool has already been in use in a number of reviews.

The frequency ramp here is around one millisecond, indicative of AMD implementing its CPPC2 management design.

The AMD Threadripper Pro 3995WX Review 280W, or Does It Turbo To More?


View All Comments

  • brucethemoose - Tuesday, February 9, 2021 - link

    There are large efforts in various communities, from Rust and C++ to Linux distros and game engines, to improve autovectorization.

    This means that more software should support AVXwhatever with minimal or no support from devs as time goes on.

    Also, one can"t always just "go to the GPU." Video encoding is a great example where this won't work.
  • RSAUser - Wednesday, February 10, 2021 - link

    NVENC seems to work pretty well. Reply
  • eastcoast_pete - Wednesday, February 10, 2021 - link

    The newest generation of NVENC (since Turing) is indeed quite capable at encoding and transcoding to AVC and h265. That ASIC has come a long way, and is really fast. However, for customized encoding situations, the story shifts; that's where CPU-based encoding comes into its own. Also, if you want AV1 encoding, we're still OOL on GPUs; if that has changed, I'd love to know. Lastly, a lot of the work these workstations are used for is CGI and editing, and for those, a combination of lots of RAM, many-core CPUs like these here and 1-2 higher end GPUs is generally what people use who do this for a living. Reply
  • GeoffreyA - Friday, February 12, 2021 - link

    NVENC, VCE, etc., work brilliantly when it comes to speed, but if one is aiming for best quality or size, it's best to go for software encoding. x264 does support a bit of OpenCL acceleration but there's hardly any gain, and it's not enabled by default. Also, even when AV1 ASICs are added, I've got a feeling it'll fall well below software encoding. Reply
  • phoenix_rizzen - Tuesday, February 9, 2021 - link

    More like, unless you absolutely NEED AVX-512 support, there's absolutely no reason to use an Intel setup.

    Pick a Ryzen, Threadripper, or EPYC depending on your needs, they'll all be a better value/performer than anything Intel currently has on the market.
  • twtech - Tuesday, February 9, 2021 - link

    It's workload-dependent, and what you're looking for. While regular TR supports ECC, it doesn't support registered ECC, which is 99% of ECC memory. The 8 memory channels also make a big difference in some workloads, such as compiling code. Also the TR Pro has a lot more PCIE lanes, as well as better support for business/corporate management.

    So I agree with your statement if you are a solo operator with a workload that is not only not very memory dependent, but not very memory-bandwidth dependent either.
  • npz - Wednesday, February 10, 2021 - link

    " While regular TR supports ECC, it doesn't support registered ECC, which is 99% of ECC memory"
    That is not true at all. Unbuffered ECC is virtually the entire market for single socket machines and has been since forever. Registered ECC is reserved only for much larger machines. Since the beginning Intel's own Pentiums to Core i3 to Celerons to Atoms that run on server chipsets--as well as AMD's own cpus starting from socket 939, AM2, etc all support only unbuffered ECC and not registered, and these are present in NAS, routers/network appliances, small single socket servers targeted for SOHO, etc. Unbuffered ECC is also much cheaper, only a small premium over non-ECC, than registered ECC. The registered dimms have the advantage of density, and why they're usually reserved for larger, usually multi socket machines or cpus designed for multi-socket even if used in single socket (including Epyc / TR Pro), but that also at a disproportionally much higher price.
  • Spunjji - Thursday, February 11, 2021 - link

    As someone who's worked in the industry for more than ten years, I can confirm this is accurate. Reply
  • twtech - Friday, February 12, 2021 - link

    Right. I've been doing this for a lot longer than 10 years, it's not really something mysterious/up for debate as the memory either exists or it doesn't, and ECC memory that is compatible with the regular non-pro TR platform is very hard to come by.

    If you want to make a case otherwise, show us where we can buy it.
  • eastcoast_pete - Wednesday, February 10, 2021 - link

    For the use case covered here (customized CPU rendering), those many cores are hard to beat. In that scenario, the main competitors for the TR pros are the upcoming, Zen 3-based Epyc and non-pro TRs. Unfortunately, Intel is still way behind. What I wonder about also is whether some of these rendering suites are also available for ARM's Neoverse arch; some of those 128+ core CPUs might be quite competitive, if the software exists. Reply

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