The Ice Lake Benchmark Preview: Inside Intel's 10nm
by Dr. Ian Cutress on August 1, 2019 9:00 AM EST- Posted in
- CPUs
- Intel
- GPUs
- 10nm
- Core
- Ice Lake
- Cannon Lake
- Sunny Cove
- 10th Gen Core
Security Updates, Improved Instruction Performance and AVX-512 Updates
With every new microarchitecture update, there are goals on several fronts: add new instructions, decrease the latency of current instructions, increase the throughput of current instructions, and remove bugs. The big headline addition for Sunny Cove and Ice Lake is AVX-512, which hasn’t yet appeared on a mainstream widely distributed consumer processor – technically we saw it in Cannon Lake, but that was a limited run CPU. Nonetheless, a lot of what went into Cannon Lake also shows up in the Sunny Cove design. To complicate matters, AVX-512 comes in plenty of different flavors. But on top of that, Intel also made a significant number of improvements to a number of instructions throughout the design.
Big thanks to InstLatX64 for his help in analyzing the benchmark results.
Security
On security, almost all the documented hardware security fixes are in place with Sunny Cove. Through the CPUID results, we can determine that SSBD is enabled, as is IA32_ARCH_CAPABILITIES, L1D_FLUSH, STIBP, IBPB/IBRS and MD_CLEAR.
This aligns with Intel’s list of Sunny Cove security improvements:
| Sunny Cove Security | |||
| AnandTech | Description | Name | Solution |
| BCB | Bound Check Bypass | Spectre V1 | Software |
| BTI | Branch Target Injection | Spectre V2 | Hardware+OS |
| RDCL | Rogue Data Cache Load | V3 | Hardware |
| RSSR | Rogue System Register Read | V3a | Hardware |
| SSB | Speculative Store Bypass | V4 | Hardware+OS |
| L1TF | Level 1 Terminal Fault | Foreshadow | Hardware |
| MFBDS | uArch Fill Buffer Data Sampling | RIDL | Hardware |
| MSBDS | uArch Store Buffer Data Sampling | Fallout | Hardware |
| MLPDS | uArch Load Port Data Sampling | - | Hardware |
| MDSUM | uArch Data Sampling Uncachable Memory | - | Hardware |
Aside from Spectre V1, which has no suitable hardware solution, almost all of the rest have been solved through hardware/firmware (Intel won’t distinguish which, but to a certain extent it doesn’t matter for new hardware). This is a step in the right direction, but of course it may have a knock-on effect, plus for anything that gets performance improvements being moved from firmware to hardware will be rolled into any advertised IPC increase.
Also on the security side is SGX, or Intel’s Software Guard Instructions. Sunny Cove now becomes Intel’s first public processor to enable both AVX-512 and SGX in the same design. Technically the first chip with both SGX and AVX-512 should have been Skylake-X, however that feature was ultimately disabled due to failing some test validation cases. But it now comes together for Sunny Cove in Ice Lake-U, which is also a consumer processor.
Instruction Improvements and AVX-512
As mentioned, Sunny Cove pulls a number of key improvements from the Cannon Lake design, despite the Cannon Lake chip having the same cache configuration as Skylake. One of the key points here is the 64-bit division throughput, which goes from a 97-cycle latency to an 18-cycle latency, blowing past AMD’s 45-cycle latency. As an ex-researcher with no idea about instruction latency or compiler options, working on high-precision math code, this speedup would have been critical.
- IDIV -> 97-cycle to 18-cycle
For the general purpose registers, we see a lot of changes, and most of them quite sizable.
| Sunny Cove GPR Changes | |||
| AnandTech | Instruction | Skylake | Sunny Cove |
| Complex LEA | Complex Load Effective Address | 3 cycle latency 1 per cycle |
1 cycle latency 2 per cycle |
| SHL/SHR | Shift Left/Right | 2 cycle latency 0.5 per cycle |
1 cycle latency 1 per cycle |
| ROL/ROR | Rotate Left/Right | 2 cycle latency 0.5 per cycle |
1 cycle latency 1 per cycle |
| SHLD/SHRD | Double Precision Shift Left/Right | 4 cycle latency 0.5 per cycle |
4 cycle latency 1 per cycle |
| 4*MOV | Four repated string MOVS | Limited instructions | 104 bits/clock All MOVS* Instructions |
In the past we’ve seen x87 instructions being regressed, made slower, as they become obsolete. For whatever reason, Sunny Cove decreases the FMUL latency from 5 cycles to 4 cycles.
The SIMD units also go through some changes:
| Sunny Cove SIMD | |||
| AnandTech | Instruction | Skylake | Sunny Cove |
| SIMD Packing | SIMD Packing now slower | 1 cycle latency 1 per cycle |
3 cycle latency 1 per cycle |
| AES* | AES Crypto Instructions (for 128-bit / 256-bit) |
4 cycle latency 2 per cycle |
3 cycle latency 2 per cycle |
| CLMUL | Carry-Less Multiplication | 7 cycle latency 1 per cycle |
6 cycle latency 1 per cycle |
| PHADD/PHSUB | Packed Horizontal Add/Subtract and Saturate |
3 cycle latency 0.5 per cycle |
2 cycle latency 1 per cycle |
| VPMOV* xmm | Vector Packed Move | 2 cycle latency 0.5 per cycle |
2 cycle latency 1 per cycle |
| VPMOV* ymm | Vector Packed Move | 4 cycle latency 0.5 per cycle |
2 cycle latency 1 per cycle |
| VPMOVZX/SX* xmm | Vector Packed Move | 1 cycle latency 1 per cycle |
1 cycle latency 2 per cycle |
| POPCNT | Microcode 50% faster than SW (under L1-D size) | ||
| REP STOS* | Repeated Store String | 62 bits/cycle | 54 bits/cycle |
| VPCONFLICT | Still Microcode Only | ||
We’ve already gone through all of the new AVX-512 instructions in our Sunny Cove microarchitecture disclosure. These include the following families:
- AVX-512_VNNI (Vector Neural Network Instructions)
- AVX-512_VBMI (Vector Byte Manipulation Instructions)
- AVX-512_VBMI2 (second level VBMI)
- AVX-512_ BITALG (bit algorithms)
- AVX-512_IFMA (Integer Fused Multiply Add)
- AVX-512_VAES (Vector AES)
- AVX-512_VPCLMULQDQ (Carry-Less Multiplacation of Long Quad Words)
- AVX-512+GFNI (Galois Field New Instructions)
- SHA (not AVX-512, but still new)
- GNA (Gaussian Neural Accelerator)
(Intel also has the GMM (Gaussian Mixture Model) inside the core since Skylake, but I’ve yet to see any information on this outside a single line in the coding manual.)
For all these new AVX-512 instructions, it’s worth noting that they can be run in 128-bit, 256-bit, or 512-bit mode, depending on the data types passed to it. Each of these can have corresponding latencies and throughputs, which often get worse when going for the 512-bit mode, but overall assuming you can fill the register with a 512-bit data type, then the overall raw processing will be faster, even with the frequency differential. This doesn’t take into account any additional overhead for entering the 512-bit power state, it should be noted.
Most of these new instructions are relatively fast, with most of them only 1-3 cycles of latency. We observed the following:
| Sunny Cove Vector Instructions | |||||
| AnandTech | Instruction | XMM | YMM | ZMM | |
| VNNI | Latency | Vector Neural Network Instructions | 5-cycle | 5-cycle | 5-cycle |
| Throughput | 2/cycle | 2/cycle | 1/cycle | ||
| VPOPCNT* | Latency | Return the number of bits set to 1 | 3-cycle | 3-cycle | 3-cycle |
| Throughput | 1/cycle | 1/cycle | 1/cycle | ||
| VPCOMPRESS* | Latency | Store Packed Data | 3-cycle | 3-cycle | 3-cycle |
| Throughput | 0.5/cycle | 0.5/cycle | 0.5/cycle | ||
| VPEXPAND* | Latency | Load Packed Data | 5-cycle | 5-cycle | 5-cycle |
| Throughput | 0.5/cycle | 0.5/cycle | 0.5/cycle | ||
| VPSHLD* | Latency | Vector Shift | 1-cycle | 1-cycle | 1-cycle |
| Throughput | 2/cycle | 2/cycle | 1/cycle | ||
| VAES* | Latency | Vector AES Instructions | 3-cycle | 3-cycle | 3-cycle |
| Throughput | 2/cycle | 2/cycle | 1/cycle | ||
| VPCLMUL | Latency | Vector Carry-Less Multiply | 6-cycle | 8-cycle | 8-cycle |
| Throughput | 1/cycle | 0.5/cycle | 0.5/cycle | ||
| GFNI | Latency | Galois Field New Instructions | 3-cycle | 3-cycle | 3-cycle |
| Throughput | 2/cycle | 2/cycle | 1/cycle | ||
For all of the common AVX2 instructions, xmm/ymm latencies and throughputs are identical to Skylake, however zmm is often a few cycles slower for DIV/SQRT variants.
Other Noticeable Observations
From our testing, we were also able to prove some of the other parts of the core, such as the added store ports and shuffle units.
Our data shows that the second store port is not identical to the first, which explains the imbalance when it comes to writes: rather than supporting 2x64-bit with loads, it only supports either 1x64-bit write, or 1x32-bit write, or 2x16-bit writes. This means we mainly see speed ups with GPR/XMM data, and the result is only a small improvement for 512-bit SCATTER instructions. Otherwise, it seems not to work with any 256-bit or 512-bit operand (you can however use it with 64-bit AVX-512 mask registers). This is going to cause a slight headache for anyone currently limited by SCATTER stores.
The new shuffle unit is only 256-bit wide. It will handle a number of integer instructions (UNPCK, PSLLDQ, SHUF*, MOVSHDUP, but not PALIGNR or PACK), but only a couple of floating point instructions (SHUFPD, SHUFPS).
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Phynaz - Saturday, August 3, 2019 - link
And it’s “than” not “then”. Perhaps your lack of grammar is part of your problem.Korguz - Saturday, August 3, 2019 - link
um ya ok sure.. anything you say...HStewart - Thursday, August 1, 2019 - link
Is useless to argue with AMD fans - they first state that 10nm is old fashion and that claims of 30% is based on 2015 Sky Lake cpus and when they find out it based on 8th generation they don't believe and then state G{U is not good enough. And that AVX 512 does not matter, bug Siggraph 2019 is going to change that.But people forget about the past, yes AMD did it 64 bit back in the older days when nobody care much about greater than 4G memory. They build memory management and we had the frequency wars with Pentium 4 days - but Intel came back with I Series and change ever. Past is be repeated again. But this time is the core wars but Ice Lake is beginning of iSeries like in those days.
Please keep in mind this is only the low power cpus that Intel has release - it only the top of iceburg.
HStewart - Thursday, August 1, 2019 - link
"G{U is not good enough. And that AVX 512 does not matter, bug Siggraph 2019"I wish we could edit, I am older so my eyes are not as good
"GPU is not good enough. And that AVX 512 does not matter, but SigGraph 2019"
Korguz - Thursday, August 1, 2019 - link
and its just a useless to argue with intel fans, right HStewart ?? you know 1st hand about that, as you are well known now to praise intel any chance you get, and seemingly forget the negative things intel has one over the years, especially the ones that cost intel a few billion dollars...HStewart - Friday, August 2, 2019 - link
Lets just keep Intel articles to Intel only and AMD articles to AMD only - not of this fan boy BS, I support Intel primary because the AMD fans are so rude to Intel supports and I will never support them because of that. I do change, I use to support only Apple and hated Android - but I change on that one primary because I saw that Apple was not changing it UI and that they require developer tools on Mac's. I not actually Intel fan, Intel user and Intel developer - that is different. I have 30 years development experience.jospoortvliet - Friday, August 2, 2019 - link
You know, nobody cares about your ‘support’. If you mean your support to help intel - it merely serves to make it look pathetic. If you have nothing intelligent to offer besides your ‘support’, whichever brand or product it is to benefit, you better just stay out of the conversation as that would improve its average quality substantially.I’m sure there are sites where comments from brand- supporting fans are appreciated. I sure as hell don’t read the comments here for that reason but to get insights and your comments just serve to make that harder as i need to weed through countless pointless conversations which involve you ‘supporting’ intel by lowering the collective intelligence of all readers here. Do everyone a favor and leave.
Korguz - Friday, August 2, 2019 - link
your are hilarious HStewart, maybe you should take your OWN advice for once.. oh wait.. you CAN'T cause you cant deal with the fact that intel isnt doing as good as it was before zen came out. when you stop with the intel fanboy BS, then maybe the rest of us will as well. no, you support intel cause you are a fanatic when it comes to them. " I not actually Intel fan " BS complete BS, and you have proved over AND over again, you are an intel fan.30 years of experience ?? BS, you dont know the DIFFERENCE between WATTS and VOLTS, and you KEEP spelling architeCture WRONG
Qasar - Friday, August 2, 2019 - link
" they first state that 10nm is old fashion and that claims of 30% is based on 2015 Sky Lake cpus and when they find out it based on 8th generation they don't believe " who is they ?? to be fair HStewart, most of intels iGP, were best suited for any thing that isnt games that arent played on facebook, or games that are a few years old, and office work. but looks like intel is trying to improve that :-)" yes AMD did it 64 bit back in the older days when nobody care much about greater than 4G memory " i can remember a few people wanting to be able to use more then 4 gigs of ram in their comps, with out having to go to server platforms, i was one of them, and a few of my friends did too.
" Please keep in mind this is only the low power cpus that Intel has release " from what i have read, seems like this is all intel can do with their current 10nm process right now, looks like intel, like with the desktop, thinks quad cores are " good enough ", cause if it isnt, why are these only quad core ? why not up the ante to 6 cores ? i guess, like the desk top, we have to wait to see if amd will do this...
RSAUser - Friday, August 2, 2019 - link
AVX512 really doesn't matter as I would find it strange for people to run such workloads on their laptops rather than on dedicated machines with way more processing power.For the common man, AVX512 does nothing though, but we can argue that most of the performance improvements don't really matter, I'm still using a device 5 years old with an i7 4720HQ and I feel no need to upgrade, only thing I am let down by is the graphics card (960M).
Intel will have a hard time convincing people to upgrade for this stuff before their machines basically keel over.