Celeron, Pentium II and III Processors

I'm going to forego listing the various models of these processors for the time being. If anyone has a real desire to see them listed, feel free to let me know. If you're running one of these processors still, I can feel for you. I still use one at work, and I only upgraded from my P3 back in March. Given the price of upgrading, though - $225 will get you a decent motherboard, 512 MB RAM, and an Athlon XP 2500+ - you really should upgrade if at all possible.

The old Pentium Pro P6 architecture was a 12-stage pipeline, more or less concluding with the Pentium III (more on that later). It had three specialized AGUs, two ALUs - one that handled simple instructions and a second one for the more complex instructions - and one FPU. The FPU also added support for SSE (which AMD lacked until the Athlon XP, but by then Intel was pushing the P4) and MMX - and they were generally faster on these instructions than AMD. That's not too surprising, considering that they created the technologies and AMD had to license them from Intel.

Intel could have certainly stuck with the design for a lot longer, as the last gasp Tualatin core offered pretty competitive performance clock for clock with the Athlon up to 1.4 GHz (the last Pentium III-S). In fact, the later 1.0A to 1.4A Celeron processors were very good overclocking chips, and a 1.1A running on a 133 MHz bus gave pretty decent performance. (I have just such a system powering my Home Theater PC.) Newer and better chipsets could have improved speed further, but Intel cut off the line and focused on pushing the Pentium 4 and NetBurst. This appears now to have been more of a marketing driven decision, although for the most part it can't be said that it was the worst idea ever.

Celeron 2 and Pentium 4 Processors

Pentium 4 and Celeron (Desktop)
P4 1.31300Willamette25610013.0X423 
C 1.71700Willamette12810017.0X478 
P4 1.41400Willamette25610014.0X423 
P4 1.41400Willamette25610014.0X478 
C 1.81800Willamette12810018.0X478 
P4 1.51500Willamette25610015.0X423 
P4 1.51500Willamette25610015.0X478 
C 2.02000Northwood12810020.0X478 
P4 1.61600Willamette25610016.0X423 
P4 1.61600Willamette25610016.0X478 
C 2.12100Northwood12810021.0X478 
P4 1.71700Willamette25610017.0X423 
P4 1.71700Willamette25610017.0X478 
C 2.22200Northwood12810022.0X478 
P4 1.61600Northwood51210016.0X478 
C 2.32300Northwood12810023.0X478 
C 2.42400Northwood12810024.0X478 
C 2.52500Northwood12810025.0X478 
P4 1.81800Northwood51210018.0X478 
C 2.62600Northwood12810026.0X478 
C 2.72700Northwood12810027.0X478 
C 2.82800Northwood12810028.0X478 
P4 2.02000Northwood51210020.0X478 
P4 2.22200Northwood51210022.0X478 
C D 3202400Prescott256133.318.0X478 
P4 2.42400Northwood51210024.0X478 
C D 3252533Prescott256133.319.0X478 
C D 325/J2533Prescott256133.319.0XT/775 
P4 2.26B2267Northwood512133.317.0X478 
C D 3302667Prescott256133.320.0X478 
C D 330/J2667Prescott256133.320.0XT/775 
P4 2.4B2400Northwood512133.318.0X478 
P4 2.62600Northwood51210026.0X478 
P4 2.4A*2400Prescott1024133.318.0X478 
C D 3352800Prescott256133.321.0X478 
C D 335/J2800Prescott256133.321.0XT/775 
P4 2.53B2533Northwood512133.319.0X478 
C D 3402933Prescott256133.322.0X478 
C D 340/J2933Prescott256133.322.0XT/775 
P4 2.4C2400Northwood51220012.0X478 
P4 2.66B2667Northwood512133.320.0X478 
P4 2.8B2800Northwood512133.321.0X478 
P4 2.6C2600Northwood51220013.0X478 
P4 2.8A*2800Prescott1024133.321.0X478 
P4 2.8E2800Prescott102420014.0X478 
P4 520/J2800Prescott102420014.0XT/775 
P4 3.06B HTT3067Northwood512133.323.0X478 
P4 2.8C2800Northwood51220014.0X478 
P4 3.0E3000Prescott102420015.0X478 
P4 530/J3000Prescott102420015.0XT/775 
P4 3.0C3000Northwood51220015.0X478 
P4 3.2E3200Prescott102420016.0X478 
P4 3.2C3200Northwood51220016.0X478 
P4 3.4E3400Prescott102420017.0X478 
P4 550/J3400Prescott102420017.0XT/775 
P4 3.4C3400Northwood51220017.0X478 
P4 560/J3600Prescott102420018.0XT/775 
P4EE 3.23200Gallatin51220016.0X4782048
P4 540/J3800Prescott102420019.0XT/775 
P4 570J3800Prescott102420019.0XT/775 
P4EE 3.43400Gallatin51220017.0X4782048
P4EE 3.43400Gallatin51220017.0XT/7752048
P4 580J4000Prescott102420020.0XT/775 
P4EE 3.463467Gallatin51226613.0XT/7752048
P4EE 3.733733Prescott204826614.0XT/775 
* Prescott 2.4A and 2.8A processors have HyperThreading Technology (HTT) disabled.
*** Front Side Bus (FSB) Speeds are "quad pumped", so Intel's FSB numbers are four times the actual bus speed on Pentium 4/Celeron, Pentium M/Celeron M, and Itanium processors. Multipliers are based off the base bus speed, not the FSB value.

NetBurst consists of a deep 20-stage pipeline coupled to an 8-stage fetch/decode unit. Due to the time spent fetching and decoding instructions, Intel created a new type of cache called a trace cache. This contained pre-decoded micro-ops, so for a large percentage of instructions, NetBurst runs as a 20-stage pipeline. Certain types of code run very well on NetBurst, while others - specifically branch-heavy code, like that seen in compilers and some games - do not. An incorrect branch prediction on P4 costs about twice as many lost cycles as an incorrect branch prediction on P3 or Athlon, which is why Intel added a more robust branch prediction unit.

The long pipeline allowed clockspeeds to scale very quickly with NetBurst. It was also a bandwidth hungry design, so increasing bus speeds combined with dual-channel memory eventually pushed the P4 beyond the reach of the Athlon XP. On the server front with the Xeon processors, the bandwidth was provided by adding L3 cache.

The Prescott further extended the NetBurst pipeline to 23 stages in addition to the 8 fetch/decode stages. For whatever reason, Intel generally describes the pipeline of the Prescott as 31 stages while only calling the earlier design a 20 stage pipeline. Besides the additional stages, Prescott doubled the L2 cache of the Northwood, added SSE3 support, and to the best of my knowledge contains deactivated x86-64 support - called EM64T by Intel and AMD64 by its creator AMD. Xeon versions of Prescott with the 64-bit support enabled are now shipping, and likely by the time XP-64 is released we will see 64-bit enabled desktop processors.

The Pentium 4 architecture also saw the introduction of Symmetric Multi-Threading (SMT) for Intel processors - they chose to call it Hyper Threading Technology (HTT). It appears to have been a part of the core from the very beginning, but Intel didn't enable the functionality until the P4 3.06 was launched, at which time it became available in the Xeon platforms as well. Later, it was enabled in all the 800 FSB "C" processors. Due to the length of the P4 pipeline, HTT allows the execution units to stay busy in the event of an incorrect branch prediction. The second thread can continue to run while the other thread recovers. In an ideal scenario, HTT could potentially increase performance by 20 or even 50 percent. In real world tests, however, rarely does it improve performance by more than 5 to 10 percent, and there are even times when it hurts performance.

With the switch to socket 775 LGA, Intel has also adopted model names. This likely has something to do with the recent difficulties Intel has encountered in scaling the NetBurst architecture to higher speeds. However, an even bigger problem is Intel's own Pentium M architecture (which is the next section). Anyway, we now have new model numbers which are supposed to reflect the overall capabilities of the chip, with higher numbers indicating more desirable chips. Comparing between families of chips should not be done based solely off the model number, however - there will certainly be instances where a 5xx chip offers better performance than a 7xx chip, and perhaps we'll also see some 3xx chips outperform their "superiors". For the time being, all of the 5xx chips are Prescott cores with 1 MB of L2 cache and an 800 MHz FSB. Future processors are also listed, and you can see where they will likely fall in the performance spectrum.

Mobile Celeron, Mobile P4, Celeron M and Pentium M Processors

Mobile Pentium/Celeron Chips**
MC 1.41400Willamette12810014.0X478M
MC 1.51500Willamette12810015.0X478M
MC 1.61600Willamette12810016.0X478M
MC 1.71700Willamette12810017.0X478M
MC 1.41400Northwood25610014.0X478M
MC 1.81800Willamette12810018.0X478M
MC 1.51500Northwood25610015.0X478M
MC 2.02000Willamette12810020.0X478M
MC 1.61600Northwood25610016.0X478M
CM 353/J900Dothan10241009.0X478M
MC 2.12100Willamette12810021.0X478M
CM 333900Banias10241009.0X478M
PM 900 (ULV)900Banias10241009.0X478M
MC 1.71700Northwood25610017.0X478M
MC 2.22200Willamette12810022.0X478M
MC 1.81800Northwood25610018.0X478M
CM 373J1000Dothan102410010.0X478M
MC 2.32300Willamette12810023.0X478M
PM 1.0 (ULV)1000Banias102410010.0X478M
MC 2.42400Willamette12810024.0X478M
MC 2.02000Northwood25610020.0X478M
PM 723/J (ULV)1000Dothan204810010.0X478M
PM 1.1 (LV)1100Banias102410011.0X478M
CM 350/J1300Dothan51210013.0X478M
MC 2.22200Northwood25610022.0X478M
PM 1.2 (LV)1200Banias102410012.0X478M
CM 3201300Banias51210013.0X478M
MC 2.42400Northwood25610024.0X478M
PM 1.31300Banias102410013.0X478M
PM 718 (LV)1300Banias102410013.0X478M
CM 3301400Banias51210014.0X478M
MC 2.52500Northwood25610025.0X478M
CM 360/J1400Dothan102410014.0X478M
MC 2.62600Northwood25610026.0X478M
CM 3401500Banias51210015.0X478M
PM 1.41400Banias102410014.0X478M
PM 713 (ULV)1400Banias102410014.0X478M
MC 2.72700Northwood25610027.0X478M
CM 370J1500Dothan102410015.0X478M
MC D 3252533Prescott256133.319.0XT/775
MC 2.82800Northwood25610028.0X478M
PM 1.51500Banias102410015.0X478M
PM 7051500Banias102410015.0X478M
PM 733/J (ULV)1400Dothan204810014.0X478M
PM 738/J (LV)1400Dothan204810014.0X478M
MC D 3302667Prescott256133.320.0XT/775
MC D 3352800Prescott256133.321.0XT/775
PM 1.61600Banias102410016.0X478M
PM 7151500Dothan204810015.0X478M
PM 758J (LV)1500Dothan204810015.0X478M
MC D 3402933Prescott256133.322.0XT/775
PM 1.71700Banias102410017.0X478M
MC D 3453066Prescott256133.323.0XT/775
MP4 2.82800Northwood512133.321.0X478M
MP4 2.8 HT2800Northwood512133.321.0X478M
PM 7351700Dothan204810017.0X478M
MC D 3503200Prescott256133.324.0XT/775
PM 730/J1600Dothan2048133.312.0X478M
MP4 5182800Prescott1024133.321.0X?478M
PM 7451800Dothan204810018.0X478M
PM 753J (ULV)1800Dothan204810018.0X478M
MP4 3.03000Northwood512133.322.5X478M
MP4 3.0 HT3000Northwood512133.322.5X478M
PM 740/J1733Dothan2048133.313.0X478M
MP4 5323067Prescott1024133.323.0X?478M
MP4 3.2 HT3200Northwood512133.324.0X478M
MP4 5383200Prescott1024133.324.0X?478M
PM 750/J1867Dothan2048133.314.0X478M
PM 7552000Dothan204810020.0X478M
PM 760/J2000Dothan2048133.315.0X478M
MP4 5523467Prescott1024133.326.0X?478M
MP4 5583600Prescott1024133.327.0X?478M
PM 770/J2133Dothan2048133.316.0X478M
PM 7652400Dothan204810024.0X478M
** There are several chips in the mobile sector. PM is for Pentium M, MP4 is the Mobile Pentium 4, CM is the Celeron M, and MC is the Mobile Celeron (P4 core).
*** Front Side Bus (FSB) Speeds are "quad pumped", so Intel's FSB numbers are four times the actual bus speed on Pentium 4/Celeron, Pentium M/Celeron M, and Itanium processors. Multipliers are based off the base bus speed, not the FSB value.

With the scaling clock speeds of the Pentium 4, not even the specially designed Mobile versions were really suited for use in laptops. (Of course, they were still used, but Intel had other plans.) Higher clockspeeds mean higher power requirements as well as increased heat output, which makes it very difficult to get increased battery life. In response to pressure from companies such as Transmeta, Intel commissioned a design team in Israel to put together a high-performance, low-power processor. The end result was the Pentium M. Where the push for high clockspeeds was the driving force behind the NetBurst design, Pentium M was targeted at reaching specific thermal requirements. While specific details are rather hard to come by, since Intel is trying to protect its lead in the Mobile space, the Pentium M appears to be a modified version of the venerable P6 architecture.

One of the improvements made to the P6 architecture was a large L2 cache, which could be powered and accessed in 32K sections. This allows large portions of the cache to be in a low-power "sleep" mode at any given time, so they get the performance benefit of a large cache without incurring as much of the usual power increase. The L1 cache was also doubled from the PIII to 32K+32K data and instruction. Floating point performance was increased with the doubling of MMX/SSE units - although this really only helped with SSE optimized code - and there were a few other architectural changes. Overall, the Pentium M is able to provide performance that's roughly the equivalent of an Athlon processor of the same clock speed, while requiring much less power. Battery life in laptops that use the Pentium M can often be 25 to 50 percent longer than equivalent laptops that use the Mobile Pentium 4, Mobile Celeron or Mobile Athlon XP chips.

The length of the above chart should be an indication of how big the mobile market has become. One of the reasons for this increase in size is likely the cut-throat conditions that exist in the desktop CPU market. Intel charges a hefty premium for most of their mobile processors since, generally speaking, anyone looking for a high-performance laptop has more money to burn. This is what I call the "mobility tax": you should only buy a laptop if portability is a primary concern; otherwise, your money will go a lot further with a desktop system. Certainly, business types that use computers for presentations and work on the road will be willing to pay this so-called tax.

With the release of the Dothan core Pentium M chips, Intel has also switched to model numbers. Here, however, there are many factors that influence the overall number. Ultra-Low Voltage processors running at lower clock speeds can end up rated higher than faster processors that require more power. This is supposed to reflect the relative desirability of certain features, as an increased battery life could be more important to some people than raw performance. Of course, Intel specifically states that the model numbers are not measures of performance, but only the technically literate are likely to know this. In their own words: "Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details."

Itanium and Itanium 2 Processors

Itanium (Server)
Itanium733Merced966611.0XPAC-4182048
Itanium733Merced966611.0XPAC-4184096
Itanium200Merced966612.0XPAC-4182048
Itanium200Merced966612.0XPAC-4184096
Itanium 2900McKinley2561009.0XPAC-6111536
Itanium 2900McKinley2561009.0XPAC-6113072
Itanium 21000McKinley25610010.0XPAC-6111536
Itanium 21000McKinley25610010.0XPAC-6113072
Itanium 2 LV1000Deerfield25610010.0XPAC-6111536
Itanium 2 LV1500Deerfield25610015.0XPAC-6111536
Itanium 21300Madison25610013.0XPAC-6113072
Itanium 21400Madison25610014.0XPAC-6114096
Itanium 21500Madison25610015.0XPAC-6116144
*** Front Side Bus (FSB) Speeds are "quad pumped", so Intel's FSB numbers are four times the actual bus speed on Pentium 4/Celeron, Pentium M/Celeron M, and Itanium processors. Multipliers are based off the base bus speed, not the FSB value.

Itanium processors are likely one of the least understood CPUs by most computer enthusiasts. Given that the cheapest models still cost over $1000, that's not really surprising. These processors are meant to target the high-end corporate world. They are often used in massively parallel processing situations, and Itaniums are capable of working in up to 512-way SMP systems. Of course, that doesn't really explain what the Itanium is.

For starters, Itanium is the way that Intel envisioned 64-bit computing, and it is built on a new instruction set dubbed IA-64 (Intel Architecture 64).. IA-64 was a clean break from x86 legacy code, and it was designed for the future. Really, its competition isn't the Xeon or Opteron CPUs, although some mistakenly compare it with these processors. Itanium is meant to compete in the high-end corporate 64-bit computing world, going up against servers based on the IBM Power4/5, HP PA-RISC, Sun UltraSparc-III, and DEC Alpha. If none of those names ring a bell, that's not very surprising. The quad-processor IBM Power4 system that was used as the main server at a company I worked for (and they had two units for redundancy) cost somewhere in the neighborhood of $500,000, and the RAID-5 array that provided data storage was another $500,000. Perhaps more important than the hardware was the service contract with IBM that helped guarantee everything stayed running. The cost of the support contract with IBM (for dozens of such setups) was supposedly around $300 million dollars a year!

The Alpha technology, interestingly enough, was purchased by Compaq, who merged with HP, and HP worked with Intel on the design of the Itanium, with the intention of using it in place of PA-RISC once it was complete. I believe that some (all?) of the Alpha technology was later transferred to Intel, most likely for use in furthering the design of the Itanium processors. Compaq/HP has continued to support this chip for the past several years, but they haven't invested a lot of money into researching new iterations of the design. This makes sense, since HP is encouraging its enterprise customers to switch to their Itanium platforms. Recently, HP announced that the 1.3 GHz (I think that was the speed) EV7 version of the Alpha chip will be the last.

These systems are often referred to as "Big Tin" systems, and they're in a league of their own. They are frequently used in systems that process huge amounts of data - their 64-bit addressing allows the use of many gigabytes of physical RAM - and they are usually optimized for input/output functions. Of course, reliability and up-time are far more important than actual performance numbers, and often once a system has been built around a specific architecture, large corporations will stick with that hardware unless there is tremendous incentive to switch to something else. Switching usually consists of several years of coding, testing, debugging, and validation - a task not to be undertaken lightly, to be sure.

For the processor design, Intel continued with their radical departure from accepted norms. Instead of a RISC or CISC approach, Intel went back to a technology that had been used in old mainframes and other computers of yore, VLIW (Very Long Instruction Word). Itanium is not a strict VLIW machine, though, as VLIW has some well known drawbacks that Intel worked to overcome, and Intel chose to call their new approach EPIC, "Explicitly Parallel Instruction Computer". In contrast to designs such as the Xeon and Opteron, which can issue up to three instructions per cycle, the Itanium 2 (forget Itanium 1 for a minute) can issue eight instructions per clock, and unlike VLIW designs, future Itanium chips could further increase the issue width without needing to recompile the code. In theory, then, a 1 GHz Itanium chip could perform roughly as fast as a 2.66 GHz Xeon/Opteron, or the 1.5 GHz Itanium 2 would be roughly as fast as a 4 GHz Xeon/Opteron. That's just theoretical performance, of course, and the overall system design will play a large role in determining how much of the potential of any system is actually realized.

To help reach that potential, Itanium chips run off a 128-bit quad-pumped system bus, using standard SDRAM (for the time being). The lower clock speeds combined with the wider bus make the SDRAM less of an issue than with high-speed desktop systems. The initial Itanium design, Merced, had four integer units (ALUs), two floating point units (FPUs), and three branch units (BRUs), two SIMD (i.e. MMX/SSE) units, and two load/store units - also called address generation units (AGUs) in other CPUs. The modified McKinley (and later) designs have six ALUs, three BRUs, two FPUs, one SIMD, two load units, and two store units - sort of like having 4 AGUs, except that they're more specialized. In addition, the McKinley has roughly three times the cache bandwidth as Merced. Merced was also a six issue design with a deeper pipeline (10 stages) and less memory bandwidth - a rather problematic design. McKinley and later designs are eight issue designs with shorter pipelines (8 stages) and more memory bandwidth. While Merced rarely made full use of its six issue design, McKinley's enhancements help it come a lot closer to issuing the maximum eight instructions per clock.

That doesn't really tell a whole lot about the architecture, and I don't really want to go much deeper than that right now. Suffice it to say that Itanium depends in a large part on compiler technology in order to reach its potential, and Intel has apparently had more difficulties in that area than they initially anticipated, but lately this seems to be less of a problem. The initial Merced design was also flawed, if you couldn't tell from my above description of the architecture, but Itanium 2 goes a long way toward rectifying the problems.

Many have called the Itanium a failure - coming up with such names as Itanic to describe the processor - especially now that AMD has launched Opteron and Intel is following suit with x86-64 support. However, they're really very different goals, and in the target market segment, Itanium is still managing to compete. Needless to say, it helps that Intel has very deep pockets thanks to the income generated from their desktop and mobile processor divisions. Itanium may or may not live in the long term, but short term Intel has plans to keep it around at least another three or four years, and they will likely keep it around longer to support existing clients. Honestly, though, I doubt any of us will ever be running an IA64 processor on our desktop systems.

A case for AMD Final Thoughts
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  • TrogdorJW - Monday, August 23, 2004 - link

    No problem, Dave - I'm not offended by any means. It's "distributed research" as far as I'm concerned. It's SMP for writers (as long as they're computer geeks, at least).

    I of course have only personally dealt with a small fraction of the total number of CPUs, since I have never worked for AMD or Intel. I'm sure there are some employees from those two companies that could provide many missing details if they chose to do so. I have to be honest that I reached the point where I just wasn't seeing any mistakes or ommissions because I had been looking at the charts and data for far too long.

    At some point in the coming months, I may look at addressing some of the remaining gaps (i.e. no P3, P2, Duron, or early Athlon CPUs are listed). Until then, I'll simply work on updating the current charts.

    One final note: I'm amazed (shocked, even) that there hasn't even been one flame about my terrible Shakespeare parody in the introduction. I did it sort of as a joke, but when my wife looked at it, she groaned in pain. You can thank Kris for removing the Timbuk-3 quote from the conclusion. Hahaha... :D

    I've got a busy night (elsewhere), so you'll probably have to wait until after 1 AM PST before I get any real updates to the pages done.
  • KristopherKubicki - Monday, August 23, 2004 - link

    The mobile athlons are better refered to as Mobile Athlon 4,

    Kristopher
  • johnsonx - Monday, August 23, 2004 - link

    Jarred,

    I totally agree with your 'aside note'. I hope you didn't take my corrections/addendums as criticism of your effort; if there is to be a 'CPU Cheatsheet', it should be as correct as possible which takes outside input.

    BTW, I kept my comments to the desktop/server arena because notebooks often use otherwise unknown variants of chips. If mobile chips are included here, then they should be listed as such. For example, it is true that 133/266 FSB Bartons do exist as Mobile AthlonXP's (and the AthlonMP 2800+ as well), but not as regular AthlonXP's. I've seen other odd variants in notebooks; probably chips meant to satisfy a particular OEM's requirements (like I could swear I've seen a notebook with Mobile AthlonXP 1000+). Then of course if you get into Mobile AXP's, then you've got that tiny uPGA socket-563 to deal with as well. What a mess...

    Regarding the 512k Clawhammer vs. Newcastle: I've now gotten the impression that the original OEM 2800+ was (and maybe still is) a Clawhammer, while all the retail ones are Newcastle. My evidence for this theory is that all 3000+ chips are 2.0Ghz, 512k cache; the original ones were 512k Clawhammers and in retail carried the part number ADA3000BOX. The newer ones are Newcastles, and carry the retail part number ADA3000AXBOX. However, the retail 2800+, which came out well after the OEM 2800+, did and still does carry the part number ADA2800BOX. This leads me to conclude that AMD adds the 'AX' when they change cores in the same model number, and further that the retail 2800+ started with the Newcastle core, as the AX has not been added to denote a core change (since I think we all agree that the retail 2800's you can buy today are indeed Newcastles).

    Regards,

    Dave
  • silentsnow - Monday, August 23, 2004 - link

    #25, #26

    There is a general consensus that all 4AP and 4AR OPN's are 512K ClawHammers. All Rev CG 512KB Athlon's are therefore Newcastle based.
  • JarredWalton - Monday, August 23, 2004 - link

    The pipeline stages for Opteron and A64 are indeed 12/17 - that has been corrected, thanks! I had heard that before, but there were quite a few sites that listed it as 10/15 still. I'll have to wait on the other bits (slightly incorrect MHz ranges) until I have a bit more time to spare.

    25/26: Yes, there is a socket 754 Newcastle now. AMD is being a little unclear on a lot of the updates, but apparently they can switch the memory controller quite easily in the core, or else the original memory controller was fully capable of dual-channel support but they somehow just turned it off. Anyway, the original 2800+ and 3000+ chips that showed up were, in all likelihood, downgraded Claw Hammer cores.

    As an aside note, the power of the Internet is rather impressive. It took a whole lot of time (as I'm sure most of you are aware) to research all the data for this article. Of course, there are bound to be mistakes (as JohnsonX and others have pointed out), but the chance of finding those alone is slim to none. It's like writing a modern software application that doesn't have any bugs! Throw something out on the Internet, however, and with thousands of eyes looking at it, your mistakes are sure to be found. :)

    I'll work on verifying and correcting some of the more greivous errors/omissions in the coming day or two. Of course, I'm also working on that little GPU chart... just don't expect die sizes or transistor counts on the chips, as they're very difficult to find. (Not so much the transistor counts, though.)
  • NinjaPirate - Monday, August 23, 2004 - link

    On the Intel Cheat Sheet, the Coppermine Celerons are marked as SMP capable, but it is the Mendocino Celerons who are SMP capable. As far as I know, nobody could get Celeron II to run SMP. Anyway, it's a very good article.
  • AkumaX - Monday, August 23, 2004 - link

    4. There were no 133Mhz FSB AthlonXP Bartons.

    Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.

    hehe, trying to keep it to the desktop, i see

    also, the Sempron seems to come in Tbred B and Thorton, and the lowest Sempron i've seen is a 2200+ (1.5ghz @ 166mhz fsb)
  • wassup4u2 - Monday, August 23, 2004 - link

    I was under the impression that the K7 had a 10-stage int pipeline and a 15 stage fp pipeline, and the one of the changes worked in the K8 was an increase to 12/17 stages, effective starting with the first K8 chip, Sledge Hammer.
  • LocutusX - Monday, August 23, 2004 - link

    #25:

    "8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct)."

    You're 98% right, I believe. The 512k Claw was only sold @ 2.0ghz, and were the "defective" 3200's remarked as 3000+. These were the ones being reviewed around December/January. Most of the new 3000+'s being sold *today*, are of course "true Newcastle". -- AFAIK!

  • johnsonx - Monday, August 23, 2004 - link

    Perhaps these are ticky-tack, but if you want it to be correct:

    1. The AthlonXP Palomino was never sold at speeds below 1333Mhz (AthlonXP 1500+).

    2. The AthlonMP Palomino was never sold at speeds below 1200Mhz (AthlonMP 1200).

    3. The Thoroughbred 'A' core never reached a speed above 1833Mhz (AthlonXP 2200+). To break beyond that, AMD had to switch to the 'B' core.

    4. There were no 133Mhz FSB AthlonXP Bartons.

    5. The AthlonMP Barton had an FSB of 133, not 166. The only MP chipset, the AMD 760MP/MPX, can only do 133 FSB.

    6. The Thoroughbred 'B' core used for the Semprons is the exact same as those used for AthlonXP's, and thus has the same die size, 84mm^2.

    7. The Socket-939 AthlonFX is a ClawHammer, not a SledgeHammer. The 'Sledge' requires Registered memory and socket-940.

    8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct).

    9. You left out the Socket-754 variant of the NewCastle. The Newcastle core starts at 1.8Ghz (S754 2800+), and so far goes up to 2.4Ghz (S754-3400+ and S939-3800+).

    Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.

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