The Kirin 980 - A Recap Overview

The Kirin 980 is the follow-up to last year’s Kirin 970. In many ways, the Kirin 980 is a much more significant chip than the previous generation chipsets from Huawei. The one thing that didn’t make the Kirin 960 and 970 as attractive, was their release schedule. The Kirin 960 suffered from being released on a 16FFC manufacturing node in a year where Qualcomm and Samsung released 10LPE SoCs – and this disadvantage for the Kirin 960 was most notable in the power and efficiency of the chipset, and was directly translated into devices which lagged behind the competition.

The Kirin 970, while closing the gap in terms of manufacturing node, on the other hand wasn’t able to catch Arm’s newest generation CPU designs due to its earlier design cycle. This meant that the chip still had to make due with Cortex A73’s versus Qualcomm’s competing Snapdragon 845 which was able to take advantage of the new Cortex A75 and A55 improvements.

This generation, HiSilicon was able to finally get manufacturing and IP design back in sync, and the Kirin 980 looks to repeat the success of the Kirin 950 from a few years ago.

HiSilicon High-End Kirin SoC Lineup
SoC Kirin 980 Kirin 970 Kirin 960
CPU 2x A76 @ 2.60 GHz
2x A76 @ 1.92 GHz
@ 512KB L2's

4x A55 @ 1.80 GHz
@ 128KB L2's

4MB DSU L3
4x A73 @ 2.36 GHz
4x A53 @ 1.84 GHz

2MB L2
4x A73 @ 2.36GHz
4x A53 @ 1.84GHz

2MB L2
GPU ARM Mali-G76MP10
@ 720 MHz
ARM Mali-G72MP12
@ 746 MHz
ARM Mali-G71MP8
@ 1037MHz
LPDDR4
Memory
4x 16-bit CH
LPDDR4X @ 2133MHz 34.1GB/s
4x 16-bit CH
LPDDR4X @ 1833 MHz
29.9GB/s
4x 16-bit CH
LPDDR4 @ 1866MHz
29.9GB/s
Storage I/F UFS 2.1 UFS 2.1 UFS 2.1
ISP/Camera New Dual ISP
+46% speed

10-bit pipeline
Dual 14-bit ISP Dual 14-bit ISP
(Improved)
Encode/Decode 2160p60 Decode   
2160p30 Encode :(
2160p60 Decode
2160p30 Encode
1080p H.264
Decode & Encode

2160p30 HEVC
Decode
Integrated Modem Kirin 980 Integrated LTE
(Category 21/18)

DL = 1400 Mbps
4x4 MIMO
3x20MHz CA, 256-QAM
(5CA no MIMO)

UL = 200 Mbps
2x2 MIMO
1x20MHz CA, 256-QAM
Kirin 970 Integrated LTE
(Category 18/13)

DL = 1200 Mbps
5x20MHz CA, 256-QAM

UL = 150 Mbps
2x20MHz CA, 64-QAM
Kirin 960 Integrated LTE
(Category 12/13)

DL = 600Mbps
4x20MHz CA, 64-QAM

UL = 150Mbps
2x20MHz CA, 64-QAM
Sensor Hub i8 i7 i6
NPU Dual @ >2x perf Yes No
Mfc. Process TSMC 7nm TSMC 10nm TSMC 16nm FFC

The new chipset sports Arm’s newest generation Cortex A76 CPUs: We covered the A76 earlier in the year, and the new Arm CPU represents a from the ground-up newly designed microarchitecture that promises great leaps in terms of performance, all while maintaining power efficiency.

The CPU complex is based on Arm’s DynamIQ cluster architecture, and we find eight cores all in all. In terms of performance cores, we find two pairs of Cortex A76’s: One pair clocks at up to 2.6GHz, while the other pair clocks at up to 1.92GHz. HiSilicon clocks the two pairs differently for two reasons: First of all, the new A76 core does go to higher power levels than previous generation cores. This means that in a mobile smartphone design, running the four cores at maximum frequency is no longer something that is feasible as it would go beyond the sustainable TDP of the platform. In order to counter-act this, the four cores are split into two clock and voltage planes, fully taking advantage of Arm’s DynamIQ cluster allowing for this. Thus, this configuration still allows for some of the cores to achieve the maximum single-threaded performance, all while reducing the power from the other pair, to remain within reasonable TDPs.

Another advantage of this configuration is that in mixed workload scenarios, the two pairs can operate at different efficiency points independently from each other, and this would allow for energy savings in workloads where there’s either one or two high-load threads, alongside some more medium load threads that would then all onto the lesser clocked A76 pair.

Alongside the four A76’s, we find four Cortex A55 cores that are dedicated for high efficiency and lower-load workloads.

In terms of cache hierarchy, HiSilicon opted for the maximum configuration for the Cortex A76’s, configuring both pairs with 512KB of L2 cache for each core. The A55 cores sported a more mid-sized 128KB L2 caches for each core. Finally, the DSU is configured with a 4MB L3, which is double the size of the previous L2 of the Kirin 970, and also double the size of the L3 of the Snapdragon 845.

A very small flagship SoC

ChipRebel is a new player in the die shot imaging business trying to get more exposure. Most notably I was impressed by the quality of their free A11 die shot last year. I’ve been talking to the folks over there and asked them what they had in plan – and fortunately enough they were able to look into publishing a teaser die shot of the Kirin 980 on their blog, alongside a teardown of the Mate 20 as well as their commercial high-resolution poly image.

I’ve already posted a quick analysis in a dedicated pipeline post last week, but let’s go over the details of the die shot again:


Die shot credit: ChipRebel

Again, the biggest surprise here comes in terms of the overall die size of the Kirin 980, coming in at a meagre 74.13mm², which represents a 30% reduction of last year’s Kirin 970, which came in at 96.72mm².  HiSilicon uses the highest flagship Kirin SoCs in a much wider range of smartphone tiers than what we’re used to, say, Qualcomm’s or Samsung’s SoCs. As such we see a lot of Honor mid-range to “premium” devices sporting the chipsets. Thus it’s quite natural that HiSilicon wants to keep the die size to a minimum, and to extract the best value possible out of the new generation process node. Still, the small die size does come as quite a surprise, and it looks like there’s room to grow in terms of a follow-up to the Kirin 980 on the same process node.

On the top left corner we can see the new Mali G76MP10 GPU. The Mali G76 drastically differs from past generation Arm GPUs in that it essentially doubles the computational capabilities of each core – in effect that one could say that the new MP10 core configuration in the Kirin 980 is about equivalent to a MP20 of the previous generation – microarchitectural improvements aside. Here HiSilicon has kept the GPU to a size of 11.97mm², among the smallest configurations we’ve seen from the vendor, and about in line with what usually Qualcomm dedicates to its Adreno GPUs in terms of block size.

On the top right, we see the CPU complex we’ve previously discussed. Here we identify the four Cortex A76 cores, with distinctive grouping into two different pairs. The distinction between the two pairs here is due to them having different physical implementations: The high frequency pair is likely synthesized to be able to achieve a higher frequency with a greater cost in power, while the lower frequency pair is optimised for power consumption, only able to achieve a lower maximum frequency.

In terms of size, the Cortex A76 cores are still largely very tiny. With the 512KB per-core L2 cache included, an A76 core measures a meagre 1.26mm², a lot smaller than the Apple A12’s Vortex core (without L2) which comes in at 2.07mm², and also a fraction of the size of Samsung’s 10nm Exynos M3 Meerkat core with the same size L2, which came in at 3.5mm² (2.52mm² without the L2).

Improved memory latencies

The memory subsystem of a SoC is fundamental to the performance of its IP blocks. The Kirin 970 here suffered a bit as it seemingly had some issues when operating at higher clock speeds, and why Huawei had opted by default to reduce the frequency in its devices. This resulted in some performance degradations, especially in memory latency sensitive workloads, as the other consequence would have been increased power consumption.

While we already know the cache sizes of the Kirin 980, as they were officially disclosed by HiSilicon, it’s still interesting to see the cache latency differences and what kind of improvements we expect to see.

Versus the Kirin 970, one thing that’s immediately to note is that DRAM latency has been significantly improved, especially over the stock behaviour of the Kirin 970. The test we’re using here is full random latency which includes all possible penalties such as TLB misses – however this is still an important metric for performance.

The private L2 cache latency of the new Cortex A76 cores are outstanding, coming in at just 4ns, less than half of the shared L2 cache latencies of the Cortex A73 in the Kirin 970. The L3 does run asynchronously to the cores and thus it sees a latency penalty, but this is still within reasonable limits.

Compared the Kirin 980 against other SoCs, we see the new design compete very well against its Android counter-parts. Interesting to see is that the L3 of the Kirin 980 seems slower than that of the Snapdragon 845, so it’s possible that HiSilicon is clocking the L3 slightly slower. The Exynos 9810 has a slight advantage in DRAM memory latency, but this quickly disappears when the core is running at more reasonable frequencies. Here we also see the Exynos suffer the worst latencies throughout its cache hierarchy.

Unfortunately for the Android SoCs, Apple’s A12 is far ahead when it comes to both cache latencies as well DRAM latency, showcasing massive advantages throughout all metrics and depths, putting the other SoCs to shame.

Introduction & Design First Cortex-A76 SoC - SPEC2006 Performance & Efficiency
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  • name99 - Friday, November 16, 2018 - link

    Please don't treat me like a child; read my comments and treat me accordingly.
    DDR as a rate (transactions) DOUBLE the clock was only relevant to the transition from SDR to DDR.
    What do you think is the difference between DDR and DDR2, or DDDR2 and DDR3, or DDR3 and DDR4?

    Part of the problem seems to be that no-one can agree on what "clock" actually refers to.
    There are at least two clocks of interest - the internal DRM clock, and the external bus clock.

    As far as I can tell:
    - DDR doubled the transfer rate over the external bus. (External bus, internal clock the same, just like SDR). Internal clock is ~100..200MHz
    - DDR2 runs the external clock at twice the internal clock.
    - DDR3 runs the external clock at 4x the internal clock. (still running from ~100 to 266MHz)

    - At DDR4 I'm no longer sure (which is part of the whole reason for this confusion).
    The obvious assumption is that the external clock is now run at 8x the internal clock; but that does NOT seem to be the case. Rather what's defined as the internal clock is now run twice as fast, so that the internal:external multiplier is still 8x, but the internal clock speeds now range from ~200 to ~400MHz.

    Meanwhile, is LPDDR following the same pattern at each generation? I haven't a clue, and can find no useful answer on the internet.
    Reply
  • anonomouse - Friday, November 16, 2018 - link

    I think the discussion of internal/external clock ratios is somewhat orthogonal to your originally posed question: the clock that is being advertised is the IO clock for the LPDDR4 modules, since they're telling you what the peak bandwidth of the module is. Commands are on the same clock but SDR instead of DDR and each command takes multiple cycles. Don't quite see what is so confusing about the 2133MHz clock though, since the way they are describing it is entirely accurate and is no different from previous practices. DDR4-3200 has a 1600MHz IO clock too.

    Also worth remembering that while pin speed is higher, individual LPDDR4 channels are 16bits vs 64bits, so it's not like the actual bandwidth is necessarily higher. This phone has 4-channels to get 34.1GB/s, which is the same bandwidth you'd get from a 2-channel DDR4-2133 system, but much more feasible to scale up capacity/channels/clocks on DDR4.
    Reply
  • frostyfiredude - Saturday, November 17, 2018 - link

    Look, I have no idea where you're going with all the internal clocks and DDR4, DDR3, etc differences so I'm not commenting. But, here are the facts on the Mate 20 Pro:

    The DRAM - Memory controller interface is clocked at 2133Mhz.
    Due to being of the DDR family, 2 bits are transferred per clock.
    Together, this mean 4266Mbits/s transfer rate per pin.
    Finally its a 64-bit bus, meaning 64 data pins. 273024Mbits/s aggregate bandwidth.
    That breaks down to 34.1GB/s.
    In standard DIMM form on your favourite PC parts store, this is advertised as DDR4-4266 or PC4-34100.
    Reply
  • ternnence - Friday, November 16, 2018 - link

    closer from ram to cpu core, higher frequency ram could get. HBM is another example. Reply
  • eastcoast_pete - Friday, November 16, 2018 - link

    @Andrei: thanks for this in-depth review! I wonder how S.LSI takes your pessimistic take on their M4; it seems they have a hard time backing away from their in-house design that doesn't seem to cut it. Also, I appreciate that you're live-updating the review with additional information; I trust reviews that add and update their findings as new data become available much more than the one-and-done style.
    Question: Did you have a chance to ask Huawei along those lines: "What is your commitment to OS updates, how quickly will you make them available, and for how many years?". Having been burned by Huawei a few years ago (promised OS update never arrived), I am still a bit once burned, twice shy. These devices are pricey, and if Huawei wants to take on Apple at Apple prices, they should mirror Apple's commitment to provide OS updates for several years.
    Reply
  • rayhydro - Friday, November 16, 2018 - link

    I'm using the mate 20 now, and I can confirm it has the same stereo setup as the mate20pro. maybe your unit's top tweeter is faulty ? Reply
  • rayhydro - Friday, November 16, 2018 - link

    I tested both side by side in the stores, both model's stereo speakers sound pretty much the same or extremely similar to my ears. I opted for mate 20 due to it's smaller notch and headphone jack :D Reply
  • lucam - Friday, November 16, 2018 - link

    I still think Mali GPU is a garbage GPU Reply
  • Lolimaster - Friday, November 16, 2018 - link

    To put it simply, at the same year, they're 1 year behind.

    Mali G76 MP10 ~ Adreno 540 (a bit faster on the mali side, maybe)
    Reply
  • lucam - Saturday, November 17, 2018 - link

    Adreno is always been better. Still think Imagination has the best solution tho Reply

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