Intel's Pentium 4 E: Prescott Arrives with Luggage

Half-Time Summary

At this point we’re done with talking about all of the microarchitectural changes that have gone into Prescott. We know it’s a lot of information so let’s go through a brief rundown of what we’ve learned so far:

- Prescott’s 31 stage pipeline by itself makes the processor significantly slower than Northwood on a clock for clock basis.
- Prescott’s L2 cache, albeit larger than Northwoods, has a higher access latency – also resulting in lower performance for the 90nm chip
- Through improvements in branch predicting, scheduling algorithms and integer execution, Intel has managed to hide a lot of the downsides to extending the pipeline.
- The large L2 cache also helps keep the pipeline full.
- SSE3 instructions will be useful down the road, but the impact given today’s software will be negligible.
- Extending the pipeline to 31 stages will allow Prescott to scale to speeds in the 4 – 5GHz range next year. It will take those speeds to make Prescott a true successor to Northwood.

With that said, let’s look at more of the common areas of discussion about the new chip.