Assessing IBM's POWER8, Part 1: A Low Level Look at Little Endian
by Johan De Gelas on July 21, 2016 8:45 AM ESTComparing with Intel's Best
Comparing CPUs in tables is always a very risky game: those simple numbers hide a lot of nuances and trade-offs. But if we approach with caution, we can still extract quite a bit of information out of it.
| Feature | IBM POWER8 |
Intel Broadwell (Xeon E5 v4) |
Intel Skylake |
| L1-I cache Associativity |
32 KB 8-way |
32 KB 8-way |
32 KB 8-way |
| L1-D cache Associativity |
64 KB 8-way |
32 KB 8-way |
32 KB 8-way |
| Outstanding L1-cache misses | 16 | 10 | 10 |
| Fetch Width | 8 instructions | 16 bytes (+/- 4-5 x86) | 16 bytes (+/- 4-5 x86) |
| Decode Width | 8 | 4 µops | 5-6* µops (*µop cache hit) |
| Issue Queue | 64+15 branch+8 CR = 87 |
60 unified | 97 unified |
| Issue Width/Cycle | 10 | 8 | 8 |
| Instructions in Flight | 224 (GCT SMT-8 modus) | 192 (ROB) | 224 (ROB) |
| Archi regs Rename regs |
32 (ST), 2x32 (SMT-2) 92 (ST), 2x92 (SMT-2) |
16 168 |
16 180 |
| Load Bandwidth (per unit) Load Queue Size |
4 per cycle 16B/cycle 44 entries |
2 per cycle 32B/cycle 72 entries |
2 per cycle 32B/cycle 72 entries |
| Store Bandwidth Store Queue Size |
2 per cycle 16B/cycle 40 entries |
1 per cycle 32B/cycle 42 entries |
1 per cycle 32B/cycle 56 entries |
| Int. Pipeline Length |
18 stages |
19 stages |
19 stages 14 stage from µop cache |
| TLB | 2048 4-way |
128I + 64D L1 1024 8-way |
128I + 64D L1 1536 8-way |
| Page Support | 4 KB, 64 KB, 16 MB, 16 GB | 4 KB, 2/4 MB, 1 GB | 4 KB, 2/4 MB, 1 GB |
Both CPUs are very wide brawny Out of Order (OoO) designs, especially compared to the ARM server SoCs.
Despite the lower decode and issue width, Intel has gone a little bit further to optimize single threaded performance than IBM. Notice that the IBM has no loop stream detector nor µop cache to reduce branch misprediction. Furthermore the load buffers of the Intel microarchitecture are deeper and the total number of instructions in flight for one thread is higher. The TLB architecture of the IBM POWER8 has more entries while Intel favors speedy address translations by offering a small level one TLB and a L2 TLB. Such a small TLB is less effective if many threads are working on huge amounts of data, but it favors a single thread that needs fast virtual to physical address translation.
On the flip side of the coin, IBM has done its homework to make sure that 2-4 threads can really boost the performance of the chip, while Intel's choices may still lead to relatively small SMT related performance gains in quite a few applications. For example, the instruction TLB, µop cache (Decode Stream Buffer) and instruction issue queues are divided in 2 when 2 threads are active. This will reduced the hit rate in the micro-op cache, and the 16 byte fetch looks a little bit on the small side. Let us see what IBM did to make sure a second thread can result in a more significant performance boost.
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nobodyblog - Thursday, July 21, 2016 - link
Please correct this error, you are saying you are comparing with BEST Intel can provide, but you did address Xeon for workloads need Xeon Phi Knight Landing which is a standalone CPU, too. If you choose correctly, the benchmark will be sooo different.IBM Power 8 is 90 GB/s, while Intel's Xeon phi knight landing (as 7290F) has a bandwidth of 400 GB/s.
IBM power 8 does above 600 gflops single precision and above 300 gflops double precision FLOPs, this is *10 in Xeon phi 7290F.
Specint: xeon phi is 1500 vs 1700 for power 8
Power and Price aside....
Thanks!
LukaP - Thursday, July 21, 2016 - link
If we start comparing different product categories, why not bring the GP100 into this as well. It will deliver 10TFLOPS of single precision and can be had for much less than any of these. But then again, there is the same caveat as the Xeon Phi. You cant actually run an OS on it, you need a host CPU and then you dispatch kernels onto the accelerator. Even if its a socketed version.smilingcrow - Thursday, July 21, 2016 - link
You can boot from newer Xeon Phi; either current or the next generation due maybe this year!LukaP - Thursday, July 21, 2016 - link
Oh really? :o that is neat, though not sure if that useful, since even highly parallel tasks usually have some IPC dependent components...Anyways have you got a source for that, would love to read more
Drumsticks - Thursday, July 21, 2016 - link
I'm a verification intern on the Phi team right now, and you can indeed boot Knight's Landing! Anandtech mentions it here: http://www.anandtech.com/show/9802/supercomputing-...nobodyblog - Friday, July 22, 2016 - link
Then you can add another xeon phi to above statistics... Xeon Phi KL is a CPU like other CPUs it does everything as mentioned even its specint is comparable, not so bad...Thanks!
tipoo - Friday, July 22, 2016 - link
Xeon Phi is x86, but it's GPU-like in nature, massively parallel for performance with low per-core performance. The IBM Power8 and other Xeons compete in highly parallel spaces like banking, but where single thread performance also still matters. Can't compare them.nobodyblog - Friday, July 22, 2016 - link
Xeon Phi Knight Landing has 3 times more single thread performance than silvermont (& knight corner).. I don't think it is so bad...The comparison is truly so, see the benchmarks, they say specint for example, or anything parallel performance, additionally, you can use a Xeon high performance with a xeon phi, there is nothing that prevents you. The benchmark is not about Database performance or parsing or anything similar, it is about this article, I don't say xeon phi is currently better positioned than xeon in these uses... But IBM's Power is not so, too, it has lots of core and lots of threads which is usable only in massive parallel uses...
Thanks!
nobodyblog - Friday, July 22, 2016 - link
On the IBM server, numactl was used to physically bind the 2, 4, or 8 copies of SPEC CPU to the first 2, 4, or 8 threads of the first core. On the Intel server, the 2 copy benchmark was bound to the first core. It is not single thread, it is a trick IBM uses to cheat in benchmarks, it is 425% percents slower than xeon in single thread.Thanks!
jospoortvliet - Tuesday, July 26, 2016 - link
The benchmarks here pit one core against one core. The IBM cores can run 1, 2, 4 or 8 threads on a single core, the Intel does 1 or 2. The 425%, not sure where that number comes from, but it isn't what shows out of these benchmarks.The benchmarks show, as described by Johan:
In single thread, the IBM does about 13% less work than the Intel core. In 2-thread mode, the IBM does about 20% more than the intel across the two threads. The intel doesn't do more than 2 threads, the IBM can and does then, on average, 43% more work across the eight threads than the Intel does with its two.
So Intel is single-thread master here, IBM is throughput king. Now if you have a HEAVILY threaded workload, with hundreds of threads and little latency requirements for each, Knights Landing or a GPU is a better choice, with their hundreds of cores. If latency is important and you can afford to use two to four threads per core the IBM performs best. If latency is everything, you keep it at 1 thread per core and the Intel Xeon is the best performer.
That is entirely ignoring cost, of course, both Intel and IBM have high and low cost solutions with their downsides and benefits. This set of benchmarks simply pitted one core against another, entirely ignoring the differences in core count (IBM 10, Intel 22) and price (Intel orders of magnitude more expensive). You'll always have to look at a bigger picture: how many cores do you get for your dollar and what are your requirements.
Performance/watt, the Intel probably wins in all area's, at least if the system is idle frequently. Without idle the IBM might be not that bad, perf/power wise.
The big take-away from this article is, though, that IBM has built a system which can be quite price-competitive with Intel in the lower-high end market. To really be able to make a choice, we'd probably need a benchmark of two price-equivalent systems. I bet the workload would make a huge difference in who wins the price/performance fight.